spi: add CS delay

src/lib.rs

@@ -16,7 +16,7 @@ pub mod tx;
 pub mod smoltcp_phy;
 
 /// Max raw frame array size
-pub const RAW_FRAME_LENGTH_MAX: usize = 0x1000;
+pub const RAW_FRAME_LENGTH_MAX: usize = 1518;
 
 pub trait EthController {
     fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError>;
@@ -29,6 +29,7 @@ pub trait EthController {
 }
 
 /// TODO: Improve these error types
+#[derive(Debug)]
 pub enum EthControllerError {
     SpiPortError,
     GeneralError,

src/spi.rs

@@ -131,13 +131,17 @@ impl <SPI: Transfer<u8>,
         match self.spi.transfer(&mut buf) {
             Ok(_) => {
                 // Disable chip select
+                cortex_m::asm::delay(10_u32);
                 self.nss.set_high();
+                cortex_m::asm::delay(5_u32);
                 Ok(buf[2])
             },
             // TODO: Maybe too naive?
             Err(_) => {
                 // Disable chip select
+                cortex_m::asm::delay(10_u32);
                 self.nss.set_high();
+                cortex_m::asm::delay(5_u32);
                 Err(SpiPortError::TransferError)
             }
         }