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lib: add write mac

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occheung 2021-01-25 11:35:00 +08:00
parent 1ce193b8aa
commit f9a126d513
1 changed files with 11 additions and 0 deletions
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11
src/lib.rs
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@ -26,6 +26,7 @@ pub trait EthController {
fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError>;
fn set_promiscuous(&mut self) -> Result<(), EthControllerError>;
fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError>;
fn write_mac_address(&mut self, mac: &[u8]) -> Result<(), EthControllerError>;
}
/// TODO: Improve these error types
@ -204,4 +205,14 @@ impl <SPI: Transfer<u8>,
mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
Ok(())
}
fn write_mac_address(&mut self, mac: &[u8]) -> Result<(), EthControllerError> {
self.spi_port.write_reg_8b(spi::addrs::MAADR1, mac[0])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR1 + 1, mac[1])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR2, mac[2])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR2 + 1, mac[3])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR3, mac[4])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR3 + 1, mac[5])?;
Ok(())
}
}