spi: owns delay

This commit is contained in:
occheung 2021-01-20 17:21:08 +08:00
parent 1ce193b8aa
commit cea9f2bf57
2 changed files with 27 additions and 17 deletions

View File

@ -19,7 +19,7 @@ pub mod smoltcp_phy;
pub const RAW_FRAME_LENGTH_MAX: usize = 1518; pub const RAW_FRAME_LENGTH_MAX: usize = 1518;
pub trait EthController { pub trait EthController {
fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError>; fn init_dev(&mut self) -> Result<(), EthControllerError>;
fn init_rxbuf(&mut self) -> Result<(), EthControllerError>; fn init_rxbuf(&mut self) -> Result<(), EthControllerError>;
fn init_txbuf(&mut self) -> Result<(), EthControllerError>; fn init_txbuf(&mut self) -> Result<(), EthControllerError>;
fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError>; fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError>;
@ -45,17 +45,19 @@ impl From<spi::SpiPortError> for EthControllerError {
/// Ethernet controller using SPI interface /// Ethernet controller using SPI interface
pub struct SpiEth<SPI: Transfer<u8>, pub struct SpiEth<SPI: Transfer<u8>,
NSS: OutputPin> { NSS: OutputPin,
spi_port: spi::SpiPort<SPI, NSS>, Delay: DelayUs<u16>> {
spi_port: spi::SpiPort<SPI, NSS, Delay>,
rx_buf: rx::RxBuffer, rx_buf: rx::RxBuffer,
tx_buf: tx::TxBuffer tx_buf: tx::TxBuffer
} }
impl <SPI: Transfer<u8>, impl <SPI: Transfer<u8>,
NSS: OutputPin> SpiEth<SPI, NSS> { NSS: OutputPin,
pub fn new(spi: SPI, nss: NSS) -> Self { Delay: DelayUs<u16>> SpiEth<SPI, NSS, Delay> {
pub fn new(spi: SPI, nss: NSS, delay: Delay) -> Self {
SpiEth { SpiEth {
spi_port: spi::SpiPort::new(spi, nss), spi_port: spi::SpiPort::new(spi, nss, delay),
rx_buf: rx::RxBuffer::new(), rx_buf: rx::RxBuffer::new(),
tx_buf: tx::TxBuffer::new() tx_buf: tx::TxBuffer::new()
} }
@ -63,8 +65,8 @@ impl <SPI: Transfer<u8>,
} }
impl <SPI: Transfer<u8>, impl <SPI: Transfer<u8>,
NSS: OutputPin> EthController for SpiEth<SPI, NSS> { NSS: OutputPin,
fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError> { Delay: DelayUs<u16>> EthController for SpiEth<SPI, NSS, Delay> {
// Write 0x1234 to EUDAST // Write 0x1234 to EUDAST
self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?; self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
// Verify that EUDAST is 0x1234 // Verify that EUDAST is 0x1234

View File

@ -1,5 +1,5 @@
use embedded_hal::{ use embedded_hal::{
blocking::spi::Transfer, blocking::{spi::Transfer, delay::DelayUs},
digital::v2::OutputPin, digital::v2::OutputPin,
}; };
@ -52,9 +52,11 @@ pub mod addrs {
/// Struct for SPI I/O interface on ENC424J600 /// Struct for SPI I/O interface on ENC424J600
/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI /// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
pub struct SpiPort<SPI: Transfer<u8>, pub struct SpiPort<SPI: Transfer<u8>,
NSS: OutputPin> { NSS: OutputPin,
Delay: DelayUs<u16>> {
spi: SPI, spi: SPI,
nss: NSS, nss: NSS,
delay: Delay,
} }
pub enum SpiPortError { pub enum SpiPortError {
@ -63,14 +65,16 @@ pub enum SpiPortError {
#[allow(unused_must_use)] #[allow(unused_must_use)]
impl <SPI: Transfer<u8>, impl <SPI: Transfer<u8>,
NSS: OutputPin> SpiPort<SPI, NSS> { NSS: OutputPin,
Delay: DelayUs<u16>> SpiPort<SPI, NSS, Delay> {
// TODO: return as Result() // TODO: return as Result()
pub fn new(spi: SPI, mut nss: NSS) -> Self { pub fn new(spi: SPI, mut nss: NSS, delay: Delay) -> Self {
nss.set_high(); nss.set_high();
SpiPort { SpiPort {
spi, spi,
nss nss,
delay
} }
} }
@ -115,6 +119,10 @@ impl <SPI: Transfer<u8>,
Ok(()) Ok(())
} }
pub fn delay_us(&mut self, duration: u16) {
self.delay.delay_us(duration)
}
// TODO: Generalise transfer functions // TODO: Generalise transfer functions
// TODO: (Make data read/write as reference to array) // TODO: (Make data read/write as reference to array)
// Currently requires 1-byte addr, read/write data is only 1-byte // Currently requires 1-byte addr, read/write data is only 1-byte
@ -131,17 +139,17 @@ impl <SPI: Transfer<u8>,
match self.spi.transfer(&mut buf) { match self.spi.transfer(&mut buf) {
Ok(_) => { Ok(_) => {
// Disable chip select // Disable chip select
cortex_m::asm::delay(10_u32); self.delay_us(1);
self.nss.set_high(); self.nss.set_high();
cortex_m::asm::delay(5_u32); self.delay_us(1);
Ok(buf[2]) Ok(buf[2])
}, },
// TODO: Maybe too naive? // TODO: Maybe too naive?
Err(_) => { Err(_) => {
// Disable chip select // Disable chip select
cortex_m::asm::delay(10_u32); self.delay_us(1);
self.nss.set_high(); self.nss.set_high();
cortex_m::asm::delay(5_u32); self.delay_us(1);
Err(SpiPortError::TransferError) Err(SpiPortError::TransferError)
} }
} }