Simplify, styling & spelling
This commit is contained in:
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e9a3a5e550
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4ba5052623
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@ -4,7 +4,7 @@
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use core::env;
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use core::env;
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extern crate panic_itm;
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extern crate panic_itm;
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use cortex_m::iprintln;
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use cortex_m::{iprintln, iprint};
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use cortex_m_rt::entry;
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use cortex_m_rt::entry;
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::digital::v2::OutputPin;
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@ -90,7 +90,7 @@ fn main() -> ! {
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let mut itm = cp.ITM;
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let mut itm = cp.ITM;
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let stim0 = &mut itm.stim[0];
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let stim0 = &mut itm.stim[0];
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iprintln!(stim0,
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iprintln!(stim0,
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"Eth TCP Server on STM32-F407 via NIC100/ENC424J600");
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"Eth TCP Server on STM32-F407 via NIC100/ENC424J600");
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// Get IP address from args
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// Get IP address from args
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@ -132,34 +132,38 @@ fn main() -> ! {
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spisel.set_low().unwrap();
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spisel.set_low().unwrap();
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// Create SPI1 for HAL
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// Create SPI1 for HAL
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let spi_eth_port = Spi::spi1(
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let spi_eth_port = Spi::spi1(
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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enc424j600::spi::interfaces::SPI_MODE,
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enc424j600::spi::interfaces::SPI_MODE,
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Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
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Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
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clocks);
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clocks);
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let mut spi_eth = enc424j600::SpiEth::new(spi_eth_port, spi1_nss);
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let mut spi_eth = enc424j600::SpiEth::new(spi_eth_port, spi1_nss);
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// Init
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// Init
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match spi_eth.init_dev(&mut delay) {
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match spi_eth.init_dev(&mut delay) {
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Ok(_) => {
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Ok(_) => {
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iprintln!(stim0, "Ethernet initialised.")
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iprintln!(stim0, "Ethernet initialized")
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}
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}
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Err(_) => {
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Err(_) => {
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panic!("Ethernet initialisation Failed!")
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panic!("Ethernet initialization failed!")
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}
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}
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}
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}
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// Setup SysTick
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// Setup SysTick
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// Reference to stm32-eth:examples/ip.rs
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// Reference to stm32-eth:examples/ip.rs
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timer_setup(delay.free(), clocks);
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timer_setup(delay.free(), clocks);
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iprintln!(stim0, "Timer initialised.");
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iprintln!(stim0, "Timer initialized");
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// Read MAC
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// Read MAC
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let mut eth_mac_addr: [u8; 6] = [0; 6];
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let mut eth_mac_addr: [u8; 6] = [0; 6];
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spi_eth.read_from_mac(&mut eth_mac_addr);
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spi_eth.read_from_mac(&mut eth_mac_addr);
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iprintln!(stim0,
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for i in 0..6 {
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"MAC Address = {:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x}",
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let byte = eth_mac_addr[i];
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eth_mac_addr[0], eth_mac_addr[1],
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match i {
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eth_mac_addr[2], eth_mac_addr[3],
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0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
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eth_mac_addr[4], eth_mac_addr[5]);
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1..=4 => iprint!(stim0, "{:02x}-", byte),
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5 => iprint!(stim0, "{:02x}\n", byte),
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_ => ()
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};
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}
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// Init Rx/Tx buffers
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// Init Rx/Tx buffers
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spi_eth.init_rxbuf();
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spi_eth.init_rxbuf();
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@ -199,10 +203,9 @@ fn main() -> ! {
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let mut socket_set = SocketSet::new(&mut socket_set_entries[..]);
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let mut socket_set = SocketSet::new(&mut socket_set_entries[..]);
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let echo_handle = socket_set.add(echo_socket);
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let echo_handle = socket_set.add(echo_socket);
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let greet_handle = socket_set.add(greet_socket);
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let greet_handle = socket_set.add(greet_socket);
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iprintln!(stim0,
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iprintln!(stim0, "TCP sockets will listen at {}", ip_addr);
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"TCP sockets will listen at {}", ip_addr);
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// Copied / modified from:
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// Copied / modified from:
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// smoltcp:examples/loopback.rs, examples/server.rs;
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// smoltcp:examples/loopback.rs, examples/server.rs;
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// stm32-eth:examples/ip.rs,
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// stm32-eth:examples/ip.rs,
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// git.m-labs.hk/M-Labs/tnetplug
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// git.m-labs.hk/M-Labs/tnetplug
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@ -220,13 +223,13 @@ fn main() -> ! {
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{
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{
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let mut socket = socket_set.get::<TcpSocket>(echo_handle);
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let mut socket = socket_set.get::<TcpSocket>(echo_handle);
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if !socket.is_open() {
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if !socket.is_open() {
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iprintln!(stim0,
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iprintln!(stim0,
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"[{}] Listening to port 1234 for echoing, time-out in 10s", instant);
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"[{}] Listening to port 1234 for echoing, time-out in 10s", instant);
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socket.listen(1234).unwrap();
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socket.listen(1234).unwrap();
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socket.set_timeout(Some(Duration::from_millis(10000)));
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socket.set_timeout(Some(Duration::from_millis(10000)));
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}
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}
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if socket.can_recv() {
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if socket.can_recv() {
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iprintln!(stim0,
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iprintln!(stim0,
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"[{}] Received packet: {:?}", instant, socket.recv(|buffer| {
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"[{}] Received packet: {:?}", instant, socket.recv(|buffer| {
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(buffer.len(), str::from_utf8(buffer).unwrap())
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(buffer.len(), str::from_utf8(buffer).unwrap())
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}));
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}));
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@ -236,7 +239,7 @@ fn main() -> ! {
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{
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{
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let mut socket = socket_set.get::<TcpSocket>(greet_handle);
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let mut socket = socket_set.get::<TcpSocket>(greet_handle);
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if !socket.is_open() {
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if !socket.is_open() {
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iprintln!(stim0,
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iprintln!(stim0,
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"[{}] Listening to port 4321 for greeting, \
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"[{}] Listening to port 4321 for greeting, \
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please connect to the port", instant);
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please connect to the port", instant);
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socket.listen(4321).unwrap();
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socket.listen(4321).unwrap();
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@ -245,13 +248,10 @@ fn main() -> ! {
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if socket.can_send() {
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if socket.can_send() {
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let greeting = "Welcome to the server demo for STM32-F407!";
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let greeting = "Welcome to the server demo for STM32-F407!";
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write!(socket, "{}\n", greeting).unwrap();
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write!(socket, "{}\n", greeting).unwrap();
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iprintln!(stim0,
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iprintln!(stim0,
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"[{}] Greeting sent, socket closed", instant);
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"[{}] Greeting sent, socket closed", instant);
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socket.close();
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socket.close();
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}
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}
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}
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}
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}
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}
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unreachable!()
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}
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}
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@ -2,7 +2,7 @@
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#![no_main]
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#![no_main]
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extern crate panic_itm;
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extern crate panic_itm;
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use cortex_m::iprintln;
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use cortex_m::{iprintln, iprint};
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use cortex_m_rt::entry;
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use cortex_m_rt::entry;
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::digital::v2::OutputPin;
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@ -39,7 +39,7 @@ fn main() -> ! {
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let mut itm = cp.ITM;
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let mut itm = cp.ITM;
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let stim0 = &mut itm.stim[0];
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let stim0 = &mut itm.stim[0];
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iprintln!(stim0,
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iprintln!(stim0,
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"Eth TX Pinging on STM32-F407 via NIC100/ENC424J600");
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"Eth TX Pinging on STM32-F407 via NIC100/ENC424J600");
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// NIC100 / ENC424J600 Set-up
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// NIC100 / ENC424J600 Set-up
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@ -57,7 +57,7 @@ fn main() -> ! {
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spisel.set_low().unwrap();
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spisel.set_low().unwrap();
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// Create SPI1 for HAL
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// Create SPI1 for HAL
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let spi_eth_port = Spi::spi1(
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let spi_eth_port = Spi::spi1(
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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enc424j600::spi::interfaces::SPI_MODE,
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enc424j600::spi::interfaces::SPI_MODE,
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Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
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Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
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clocks);
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clocks);
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@ -65,25 +65,25 @@ fn main() -> ! {
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// Init
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// Init
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match spi_eth.init_dev(&mut delay) {
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match spi_eth.init_dev(&mut delay) {
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Ok(_) => {
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Ok(_) => {
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iprintln!(stim0, "Ethernet initialised.")
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iprintln!(stim0, "Ethernet initialized")
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}
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}
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Err(_) => {
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Err(_) => {
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panic!("Ethernet initialisation Failed!")
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panic!("Ethernet initialization failed!")
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}
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}
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}
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}
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// Read MAC
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// Read MAC
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let mut eth_mac_addr: [u8; 6] = [0; 6];
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let mut eth_mac_addr: [u8; 6] = [0; 6];
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spi_eth.read_from_mac(&mut eth_mac_addr);
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spi_eth.read_from_mac(&mut eth_mac_addr);
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iprintln!(stim0,
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for i in 0..6 {
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"MAC Address = {:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x}",
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let byte = eth_mac_addr[i];
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eth_mac_addr[0], eth_mac_addr[1],
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match i {
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eth_mac_addr[2], eth_mac_addr[3],
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0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
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eth_mac_addr[4], eth_mac_addr[5]);
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1..=4 => iprint!(stim0, "{:02x}-", byte),
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// Set to promiscuous mode
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5 => iprint!(stim0, "{:02x}\n", byte),
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spi_eth.set_promiscuous();
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_ => ()
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iprintln!(stim0,
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};
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"Promiscuous Mode ON");
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}
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// Init Rx/Tx buffers
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// Init Rx/Tx buffers
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spi_eth.init_rxbuf();
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spi_eth.init_rxbuf();
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loop {
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loop {
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let mut eth_tx_packet = enc424j600::tx::TxPacket::new();
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let mut eth_tx_packet = enc424j600::tx::TxPacket::new();
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eth_tx_packet.update_frame(ð_tx_dat, 64);
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eth_tx_packet.update_frame(ð_tx_dat, 64);
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iprintln!(stim0,
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iprint!(stim0,
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"Sending packet (len={:}): \
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"Sending packet (len={:}): ", eth_tx_packet.get_frame_length());
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dest={:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x} \
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for i in 0..20 {
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src={:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x} \
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let byte = eth_tx_packet.get_frame_byte(i);
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data={:02x}{:02x}{:02x}{:02x} {:02x}{:02x}{:02x}{:02x} ...",
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match i {
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eth_tx_packet.get_frame_length(),
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0 => iprint!(stim0, "dest={:02x}-", byte),
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eth_tx_packet.get_frame_byte(0), eth_tx_packet.get_frame_byte(1), eth_tx_packet.get_frame_byte(2),
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6 => iprint!(stim0, "src={:02x}-", byte),
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eth_tx_packet.get_frame_byte(3), eth_tx_packet.get_frame_byte(4), eth_tx_packet.get_frame_byte(5),
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12 => iprint!(stim0, "data={:02x}", byte),
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eth_tx_packet.get_frame_byte(6), eth_tx_packet.get_frame_byte(7), eth_tx_packet.get_frame_byte(8),
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1..=4 | 7..=10 => iprint!(stim0, "{:02x}-", byte),
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eth_tx_packet.get_frame_byte(9), eth_tx_packet.get_frame_byte(10), eth_tx_packet.get_frame_byte(11),
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13..=14 | 16..=18 => iprint!(stim0, "{:02x}", byte),
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eth_tx_packet.get_frame_byte(12), eth_tx_packet.get_frame_byte(13),
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5 | 11 | 15 => iprint!(stim0, "{:02x} ", byte),
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eth_tx_packet.get_frame_byte(14), eth_tx_packet.get_frame_byte(15),
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19 => iprint!(stim0, "{:02x} ...\n", byte),
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eth_tx_packet.get_frame_byte(16), eth_tx_packet.get_frame_byte(17),
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_ => ()
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eth_tx_packet.get_frame_byte(18), eth_tx_packet.get_frame_byte(19)
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};
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);
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}
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spi_eth.send_raw_packet(ð_tx_packet);
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spi_eth.send_raw_packet(ð_tx_packet);
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iprintln!(stim0,
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iprintln!(stim0, "Packet sent");
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"Packet sent");
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delay.delay_ms(100_u32);
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delay.delay_ms(100_u32);
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}
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}
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unreachable!()
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}
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}
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20
src/lib.rs
20
src/lib.rs
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@ -40,14 +40,14 @@ impl From<spi::SpiPortError> for EthControllerError {
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}
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}
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/// Ethernet controller using SPI interface
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/// Ethernet controller using SPI interface
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pub struct SpiEth<SPI: Transfer<u8>,
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pub struct SpiEth<SPI: Transfer<u8>,
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NSS: OutputPin> {
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NSS: OutputPin> {
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spi_port: spi::SpiPort<SPI, NSS>,
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spi_port: spi::SpiPort<SPI, NSS>,
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rx_buf: rx::RxBuffer,
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rx_buf: rx::RxBuffer,
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tx_buf: tx::TxBuffer
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tx_buf: tx::TxBuffer
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}
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}
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impl <SPI: Transfer<u8>,
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impl <SPI: Transfer<u8>,
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NSS: OutputPin> SpiEth<SPI, NSS> {
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NSS: OutputPin> SpiEth<SPI, NSS> {
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pub fn new(spi: SPI, nss: NSS) -> Self {
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pub fn new(spi: SPI, nss: NSS) -> Self {
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SpiEth {
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SpiEth {
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@ -58,14 +58,14 @@ impl <SPI: Transfer<u8>,
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}
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}
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}
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}
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impl <'c, SPI: Transfer<u8>,
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impl <'c, SPI: Transfer<u8>,
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NSS: OutputPin> EthController<'c> for SpiEth<SPI, NSS> {
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NSS: OutputPin> EthController<'c> for SpiEth<SPI, NSS> {
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fn init_dev(&mut self, delay: &mut dyn DelayUs<u16>) -> Result<(), EthControllerError> {
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fn init_dev(&mut self, delay: &mut dyn DelayUs<u16>) -> Result<(), EthControllerError> {
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// Write 0x1234 to EUDAST
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// Write 0x1234 to EUDAST
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self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
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self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
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// Verify that EUDAST is 0x1234
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// Verify that EUDAST is 0x1234
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let mut eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
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let mut eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
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if eudast != 0x1234 {
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if eudast != 0x1234 {
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return Err(EthControllerError::GeneralError)
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return Err(EthControllerError::GeneralError)
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}
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}
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// Poll CLKRDY (ESTAT<12>) to check if it is set
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// Poll CLKRDY (ESTAT<12>) to check if it is set
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@ -80,7 +80,7 @@ impl <'c, SPI: Transfer<u8>,
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delay.delay_us(25_u16);
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delay.delay_us(25_u16);
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// Verify that EUDAST is 0x0000
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// Verify that EUDAST is 0x0000
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eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
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eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
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if eudast != 0x0000 {
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if eudast != 0x0000 {
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return Err(EthControllerError::GeneralError)
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return Err(EthControllerError::GeneralError)
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}
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}
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// Wait for 256us
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// Wait for 256us
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@ -110,7 +110,7 @@ impl <'c, SPI: Transfer<u8>,
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/// Receive the next packet and return it
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/// Receive the next packet and return it
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/// Set is_poll to true for returning until PKTIF is set;
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/// Set is_poll to true for returning until PKTIF is set;
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/// Set is_poll to false for returning Err when PKTIF is not set
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/// Set is_poll to false for returning Err when PKTIF is not set
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fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
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fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
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// Poll PKTIF (EIR<4>) to check if it is set
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// Poll PKTIF (EIR<4>) to check if it is set
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loop {
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loop {
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let eir = self.spi_port.read_reg_16b(spi::addrs::EIR)?;
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let eir = self.spi_port.read_reg_16b(spi::addrs::EIR)?;
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@ -156,7 +156,7 @@ impl <'c, SPI: Transfer<u8>,
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// Set EGPWRPT pointer to next_addr
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// Set EGPWRPT pointer to next_addr
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self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
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self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
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// Copy packet data to SRAM Buffer
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// Copy packet data to SRAM Buffer
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// 1-byte Opcode is included
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// 1-byte Opcode is included
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let mut txdat_buf: [u8; tx::RAW_FRAME_LENGTH_MAX + 1] = [0; tx::RAW_FRAME_LENGTH_MAX + 1];
|
let mut txdat_buf: [u8; tx::RAW_FRAME_LENGTH_MAX + 1] = [0; tx::RAW_FRAME_LENGTH_MAX + 1];
|
||||||
packet.write_frame_to(&mut txdat_buf[1..]);
|
packet.write_frame_to(&mut txdat_buf[1..]);
|
||||||
self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
|
self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
|
||||||
|
@ -175,15 +175,15 @@ impl <'c, SPI: Transfer<u8>,
|
||||||
// TODO: Read ETXSTAT to understand Ethernet transmission status
|
// TODO: Read ETXSTAT to understand Ethernet transmission status
|
||||||
// (See: Register 9-2, ENC424J600 Data Sheet)
|
// (See: Register 9-2, ENC424J600 Data Sheet)
|
||||||
// Update TX buffer start address
|
// Update TX buffer start address
|
||||||
self.tx_buf.set_next_addr((self.tx_buf.get_next_addr() + packet.get_frame_length() as u16) %
|
self.tx_buf.set_next_addr((self.tx_buf.get_next_addr() + packet.get_frame_length() as u16) %
|
||||||
tx::GPBUFEN_DEFAULT);
|
tx::GPBUFEN_DEFAULT);
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Set controller to Promiscuous Mode
|
/// Set controller to Promiscuous Mode
|
||||||
fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
|
fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
|
||||||
// From Section 10.12, ENC424J600 Data Sheet:
|
// From Section 10.12, ENC424J600 Data Sheet:
|
||||||
// "To accept all incoming frames regardless of content (Promiscuous mode),
|
// "To accept all incoming frames regardless of content (Promiscuous mode),
|
||||||
// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
|
// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
|
||||||
let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
|
let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
|
||||||
self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
|
self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
|
||||||
|
|
20
src/spi.rs
20
src/spi.rs
|
@ -51,7 +51,7 @@ pub mod addrs {
|
||||||
|
|
||||||
/// Struct for SPI I/O interface on ENC424J600
|
/// Struct for SPI I/O interface on ENC424J600
|
||||||
/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
|
/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
|
||||||
pub struct SpiPort<SPI: Transfer<u8>,
|
pub struct SpiPort<SPI: Transfer<u8>,
|
||||||
NSS: OutputPin> {
|
NSS: OutputPin> {
|
||||||
spi: SPI,
|
spi: SPI,
|
||||||
nss: NSS,
|
nss: NSS,
|
||||||
|
@ -62,14 +62,14 @@ pub enum SpiPortError {
|
||||||
}
|
}
|
||||||
|
|
||||||
#[allow(unused_must_use)]
|
#[allow(unused_must_use)]
|
||||||
impl <SPI: Transfer<u8>,
|
impl <SPI: Transfer<u8>,
|
||||||
NSS: OutputPin> SpiPort<SPI, NSS> {
|
NSS: OutputPin> SpiPort<SPI, NSS> {
|
||||||
// TODO: return as Result()
|
// TODO: return as Result()
|
||||||
pub fn new(spi: SPI, mut nss: NSS) -> Self {
|
pub fn new(spi: SPI, mut nss: NSS) -> Self {
|
||||||
nss.set_high();
|
nss.set_high();
|
||||||
|
|
||||||
SpiPort {
|
SpiPort {
|
||||||
spi,
|
spi,
|
||||||
nss
|
nss
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -88,7 +88,7 @@ impl <SPI: Transfer<u8>,
|
||||||
}
|
}
|
||||||
|
|
||||||
// Currently requires manual slicing (buf[1..]) for the data read back
|
// Currently requires manual slicing (buf[1..]) for the data read back
|
||||||
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
|
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
|
||||||
-> Result<(), SpiPortError> {
|
-> Result<(), SpiPortError> {
|
||||||
let r_valid = self.r_n(buf, opcodes::RERXDATA, data_length)?;
|
let r_valid = self.r_n(buf, opcodes::RERXDATA, data_length)?;
|
||||||
Ok(r_valid)
|
Ok(r_valid)
|
||||||
|
@ -96,7 +96,7 @@ impl <SPI: Transfer<u8>,
|
||||||
|
|
||||||
// Currenly requires actual data to be stored in buf[1..] instead of buf[0..]
|
// Currenly requires actual data to be stored in buf[1..] instead of buf[0..]
|
||||||
// TODO: Maybe better naming?
|
// TODO: Maybe better naming?
|
||||||
pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
|
pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
|
||||||
-> Result<(), SpiPortError> {
|
-> Result<(), SpiPortError> {
|
||||||
let w_valid = self.w_n(buf, opcodes::WEGPDATA, data_length)?;
|
let w_valid = self.w_n(buf, opcodes::WEGPDATA, data_length)?;
|
||||||
Ok(w_valid)
|
Ok(w_valid)
|
||||||
|
@ -118,7 +118,7 @@ impl <SPI: Transfer<u8>,
|
||||||
// TODO: Generalise transfer functions
|
// TODO: Generalise transfer functions
|
||||||
// TODO: (Make data read/write as reference to array)
|
// TODO: (Make data read/write as reference to array)
|
||||||
// Currently requires 1-byte addr, read/write data is only 1-byte
|
// Currently requires 1-byte addr, read/write data is only 1-byte
|
||||||
fn rw_addr_u8(&mut self, opcode: u8, addr: u8, data: u8)
|
fn rw_addr_u8(&mut self, opcode: u8, addr: u8, data: u8)
|
||||||
-> Result<u8, SpiPortError> {
|
-> Result<u8, SpiPortError> {
|
||||||
// Enable chip select
|
// Enable chip select
|
||||||
self.nss.set_low();
|
self.nss.set_low();
|
||||||
|
@ -144,11 +144,11 @@ impl <SPI: Transfer<u8>,
|
||||||
}
|
}
|
||||||
|
|
||||||
// TODO: Generalise transfer functions
|
// TODO: Generalise transfer functions
|
||||||
// Currently does NOT accept addr, read data is N-byte long
|
// Currently does NOT accept addr, read data is N-byte long
|
||||||
// Returns a reference to the data returned
|
// Returns a reference to the data returned
|
||||||
// Note: buf must be at least (data_length + 1)-byte long
|
// Note: buf must be at least (data_length + 1)-byte long
|
||||||
// TODO: Check and raise error for array size < (data_length + 1)
|
// TODO: Check and raise error for array size < (data_length + 1)
|
||||||
fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
|
fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
|
||||||
-> Result<(), SpiPortError> {
|
-> Result<(), SpiPortError> {
|
||||||
// Enable chip select
|
// Enable chip select
|
||||||
self.nss.set_low();
|
self.nss.set_low();
|
||||||
|
@ -171,7 +171,7 @@ impl <SPI: Transfer<u8>,
|
||||||
|
|
||||||
// Note: buf[0] is currently reserved for opcode to overwrite
|
// Note: buf[0] is currently reserved for opcode to overwrite
|
||||||
// TODO: Actual data should start from buf[0], not buf[1]
|
// TODO: Actual data should start from buf[0], not buf[1]
|
||||||
fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
|
fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
|
||||||
-> Result<(), SpiPortError> {
|
-> Result<(), SpiPortError> {
|
||||||
// Enable chip select
|
// Enable chip select
|
||||||
self.nss.set_low();
|
self.nss.set_low();
|
||||||
|
|
|
@ -36,7 +36,7 @@ impl TxBuffer {
|
||||||
pub fn get_next_addr(& self) -> u16{
|
pub fn get_next_addr(& self) -> u16{
|
||||||
self.next_addr
|
self.next_addr
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn set_tail_addr(&mut self, addr: u16) {
|
pub fn set_tail_addr(&mut self, addr: u16) {
|
||||||
self.tail_addr = addr;
|
self.tail_addr = addr;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue