204 lines
8.3 KiB
Rust
204 lines
8.3 KiB
Rust
#![no_std]
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pub mod spi;
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use embedded_hal::{
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blocking::{
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spi::Transfer,
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delay::DelayUs,
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},
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digital::v2::OutputPin,
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};
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pub mod rx;
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pub mod tx;
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#[cfg(feature="smoltcp")]
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pub mod smoltcp_phy;
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pub trait EthController<'c> {
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fn init_dev(&mut self, delay: &mut dyn DelayUs<u16>) -> Result<(), EthControllerError>;
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fn init_rxbuf(&mut self) -> Result<(), EthControllerError>;
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fn init_txbuf(&mut self) -> Result<(), EthControllerError>;
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fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError>;
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fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError>;
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fn set_promiscuous(&mut self) -> Result<(), EthControllerError>;
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fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError>;
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}
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/// TODO: Improve these error types
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pub enum EthControllerError {
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SpiPortError,
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GeneralError,
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// TODO: Better name?
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NoRxPacketError
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}
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impl From<spi::SpiPortError> for EthControllerError {
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fn from(_: spi::SpiPortError) -> EthControllerError {
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EthControllerError::SpiPortError
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}
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}
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/// Ethernet controller using SPI interface
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pub struct SpiEth<SPI: Transfer<u8>,
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NSS: OutputPin> {
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spi_port: spi::SpiPort<SPI, NSS>,
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rx_buf: rx::RxBuffer,
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tx_buf: tx::TxBuffer
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}
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impl <SPI: Transfer<u8>,
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NSS: OutputPin> SpiEth<SPI, NSS> {
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pub fn new(spi: SPI, nss: NSS) -> Self {
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SpiEth {
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spi_port: spi::SpiPort::new(spi, nss),
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rx_buf: rx::RxBuffer::new(),
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tx_buf: tx::TxBuffer::new()
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}
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}
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}
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impl <'c, SPI: Transfer<u8>,
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NSS: OutputPin> EthController<'c> for SpiEth<SPI, NSS> {
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fn init_dev(&mut self, delay: &mut dyn DelayUs<u16>) -> Result<(), EthControllerError> {
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// Write 0x1234 to EUDAST
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self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
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// Verify that EUDAST is 0x1234
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let mut eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
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if eudast != 0x1234 {
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return Err(EthControllerError::GeneralError)
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}
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// Poll CLKRDY (ESTAT<12>) to check if it is set
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loop {
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let estat = self.spi_port.read_reg_16b(spi::addrs::ESTAT)?;
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if estat & 0x1000 == 0x1000 { break }
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}
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// Set ETHRST (ECON2<4>) to 1
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let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?;
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self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?;
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// Wait for 25us
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delay.delay_us(25_u16);
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// Verify that EUDAST is 0x0000
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eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
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if eudast != 0x0000 {
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return Err(EthControllerError::GeneralError)
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}
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// Wait for 256us
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delay.delay_us(256_u16);
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Ok(())
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}
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fn init_rxbuf(&mut self) -> Result<(), EthControllerError> {
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// Set ERXST pointer
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self.spi_port.write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_wrap_addr())?;
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// Set ERXTAIL pointer
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self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_tail_addr())?;
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// Set MAMXFL to maximum number of bytes in each accepted packet
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self.spi_port.write_reg_16b(spi::addrs::MAMXFL, rx::RAW_FRAME_LENGTH_MAX as u16)?;
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// Enable RXEN (ECON1<0>)
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let econ1 = self.spi_port.read_reg_16b(spi::addrs::ECON1)?;
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self.spi_port.write_reg_16b(spi::addrs::ECON1, 0x1 | (econ1 & 0xfffe))?;
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Ok(())
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}
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fn init_txbuf(&mut self) -> Result<(), EthControllerError> {
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// Set EGPWRPT pointer
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self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, 0x0000)?;
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Ok(())
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}
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/// Receive the next packet and return it
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/// Set is_poll to true for returning until PKTIF is set;
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/// Set is_poll to false for returning Err when PKTIF is not set
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fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
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// Poll PKTIF (EIR<4>) to check if it is set
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loop {
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let eir = self.spi_port.read_reg_16b(spi::addrs::EIR)?;
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if eir & 0x40 == 0x40 { break }
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if !is_poll {
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return Err(EthControllerError::NoRxPacketError)
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}
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}
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// Set ERXRDPT pointer to next_addr
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self.spi_port.write_reg_16b(spi::addrs::ERXRDPT, self.rx_buf.get_next_addr())?;
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// Read 2 bytes to update next_addr
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let mut next_addr_buf = [0; 3];
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self.spi_port.read_rxdat(&mut next_addr_buf, 2)?;
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self.rx_buf.set_next_addr((next_addr_buf[1] as u16) | ((next_addr_buf[2] as u16) << 8));
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// Read 6 bytes to update rsv
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let mut rsv_buf = [0; 7];
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self.spi_port.read_rxdat(&mut rsv_buf, 6)?;
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// Construct an RxPacket
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// TODO: can we directly assign to fields instead of using functions?
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let mut rx_packet = rx::RxPacket::new();
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// Get and update frame length
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rx_packet.write_to_rsv(&rsv_buf[1..]);
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rx_packet.update_frame_length();
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// Read frame bytes
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let mut frame_buf = [0; rx::RAW_FRAME_LENGTH_MAX];
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self.spi_port.read_rxdat(&mut frame_buf, rx_packet.get_frame_length())?;
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rx_packet.copy_frame_from(&frame_buf[1..]);
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// Set ERXTAIL pointer to (next_addr - 2)
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if self.rx_buf.get_next_addr() > rx::ERXST_DEFAULT {
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self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_next_addr() - 2)?;
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} else {
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self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
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}
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// Set PKTDEC (ECON1<88>) to decrement PKTCNT
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let econ1_hi = self.spi_port.read_reg_8b(spi::addrs::ECON1 + 1)?;
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self.spi_port.write_reg_8b(spi::addrs::ECON1 + 1, 0x01 | (econ1_hi & 0xfe))?;
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// Return the RxPacket
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Ok(rx_packet)
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}
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/// Send an established packet
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fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError> {
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// Set EGPWRPT pointer to next_addr
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self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
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// Copy packet data to SRAM Buffer
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// 1-byte Opcode is included
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let mut txdat_buf: [u8; tx::RAW_FRAME_LENGTH_MAX + 1] = [0; tx::RAW_FRAME_LENGTH_MAX + 1];
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packet.write_frame_to(&mut txdat_buf[1..]);
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self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
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// Set ETXST to packet start address
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self.spi_port.write_reg_16b(spi::addrs::ETXST, self.tx_buf.get_next_addr())?;
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// Set ETXLEN to packet length
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self.spi_port.write_reg_16b(spi::addrs::ETXLEN, packet.get_frame_length() as u16)?;
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// Set TXRTS (ECON1<1>) to start transmission
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let mut econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
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self.spi_port.write_reg_8b(spi::addrs::ECON1, 0x02 | (econ1_lo & 0xfd))?;
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// Poll TXRTS (ECON1<1>) to check if it is reset
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loop {
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econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
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if econ1_lo & 0x02 == 0x02 { break }
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}
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// TODO: Read ETXSTAT to understand Ethernet transmission status
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// (See: Register 9-2, ENC424J600 Data Sheet)
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// Update TX buffer start address
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self.tx_buf.set_next_addr((self.tx_buf.get_next_addr() + packet.get_frame_length() as u16) %
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tx::GPBUFEN_DEFAULT);
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Ok(())
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}
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/// Set controller to Promiscuous Mode
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fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
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// From Section 10.12, ENC424J600 Data Sheet:
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// "To accept all incoming frames regardless of content (Promiscuous mode),
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// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
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let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
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self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
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Ok(())
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}
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/// Read MAC to [u8; 6]
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fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError> {
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mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
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mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
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mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
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mac[3] = self.spi_port.read_reg_8b(spi::addrs::MAADR2 + 1)?;
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mac[4] = self.spi_port.read_reg_8b(spi::addrs::MAADR3)?;
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mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
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Ok(())
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}
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}
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