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init: use delay from internal spi

This commit is contained in:
occheung 2021-01-20 17:27:02 +08:00
parent cea9f2bf57
commit 056f812e60
1 changed files with 3 additions and 2 deletions
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5
src/lib.rs
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@ -67,6 +67,7 @@ impl <SPI: Transfer<u8>,
impl <SPI: Transfer<u8>, impl <SPI: Transfer<u8>,
NSS: OutputPin, NSS: OutputPin,
Delay: DelayUs<u16>> EthController for SpiEth<SPI, NSS, Delay> { Delay: DelayUs<u16>> EthController for SpiEth<SPI, NSS, Delay> {
fn init_dev(&mut self) -> Result<(), EthControllerError> {
// Write 0x1234 to EUDAST // Write 0x1234 to EUDAST
self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?; self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
// Verify that EUDAST is 0x1234 // Verify that EUDAST is 0x1234
@ -83,14 +84,14 @@ impl <SPI: Transfer<u8>,
let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?; let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?;
self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?; self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?;
// Wait for 25us // Wait for 25us
delay.delay_us(25_u16); self.spi_port.delay_us(25_u16);
// Verify that EUDAST is 0x0000 // Verify that EUDAST is 0x0000
eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?; eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
if eudast != 0x0000 { if eudast != 0x0000 {
return Err(EthControllerError::GeneralError) return Err(EthControllerError::GeneralError)
} }
// Wait for 256us // Wait for 256us
delay.delay_us(256_u16); self.spi_port.delay_us(256_u16);
Ok(()) Ok(())
} }