5800496425
coredevice/adf5356_reg: port to NAC3
2021-11-24 16:54:58 +08:00
9423428bb0
drtio: fix crc32 offset address
2021-11-24 12:00:56 +08:00
29f42ccd8a
coredevice/mirny: port to NAC3
2021-11-23 17:13:43 +08:00
f5a5b7a22a
examples: add nac3devices
2021-11-23 16:41:29 +08:00
3a6fcd069d
remove old examples
2021-11-23 16:37:40 +08:00
d8e1a22bdf
coredevice/ad53xx: remove problematic default param
2021-11-23 16:12:36 +08:00
34789767f0
firmware: fix compilation warning
2021-11-22 18:23:28 +08:00
bd95d9cf3d
coredevice/zotino: port to NAC3
2021-11-19 19:13:50 +08:00
64877c0588
fix Python 3.9 compatibility
2021-11-19 18:18:24 +08:00
aa5f667ad8
ad9912: increase slack (no kernel invariants in NAC3 yet?)
2021-11-19 12:47:52 +08:00
cc1080e055
ad9912: fix frequency_to_ftw
2021-11-19 12:42:08 +08:00
b49f813b17
artiq_flash: ignore checking non-RTM artifacts if unused
2021-11-18 16:59:32 +08:00
f4acf04405
coredevice: fix run method
2021-11-16 18:32:14 +08:00
Peter Drmota
20e079a381
AD9910 driver feature extension and SUServo IIR readability ( #1500 )
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* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync
* SUServo: Wrap CPLD and DDS devices in a list
* SUServo: Refactor [nfc]
Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
2021-11-15 12:09:16 +08:00
222968d68b
coredevice: reinstate AugAssign methods
2021-11-13 12:42:13 +08:00
38e554fe98
artiq_run: fix ELF handling
2021-11-12 19:57:48 +08:00
75dad8090f
Merge branch 'master' into nac3
2021-11-12 19:46:37 +08:00
95eb218112
import_cache: read files only once
2021-11-11 20:42:49 +08:00
1ea3cf48d6
fix core.run invokation
2021-11-11 20:35:45 +08:00
5a3bf4894f
reinstate import_cache hack ( #416 )
2021-11-11 20:35:06 +08:00
c7cca11ad1
update NAC3
2021-11-11 16:32:37 +08:00
a8129093df
artiq_run: port to NAC3 (WIP)
2021-11-10 21:31:03 +08:00
df87cc88d6
coredevice/ad9912: port to NAC3
2021-11-10 21:27:06 +08:00
93f24c9f94
coredevice/urukul: port to NAC3
2021-11-10 19:01:44 +08:00
31955d0c7a
coredevice/spi2: port to NAC3
2021-11-10 17:23:44 +08:00
b7313ddc32
coredevice/rtio: fix tuple annotation
2021-11-10 15:32:07 +08:00
262cd62544
examples/blink_forever: port to NAC3
2021-11-10 13:59:59 +08:00
2f031285a4
coredevice/ttl: port to NAC3
2021-11-10 13:58:54 +08:00
deb8a77464
coredevice/rtio: port to NAC3
2021-11-10 13:57:03 +08:00
8f596ed04f
coredevice: fix typing problems
2021-11-10 12:37:05 +08:00
c8ebd80fe2
NAC3 integration WIP
2021-11-10 12:18:20 +08:00
db3e5e83e6
bump misoc
2021-11-08 16:59:08 +08:00
09945ecc4d
gateware: fix drtio/dma tests
2021-11-08 16:59:08 +08:00
02119282b8
build_soc: build VexRiscv_G if not kasli v1.x
2021-11-08 16:59:08 +08:00
750b0ce46d
ddb_temp: select appropriate compiler target
2021-11-08 16:59:08 +08:00
531670d6c5
dyld: check ABI
2021-11-08 16:59:08 +08:00
0f660735bf
ll_gen: adjust csr address by detecting target class
2021-11-08 16:59:08 +08:00
0755757601
compiler/tb: use FPU
2021-11-08 16:59:08 +08:00
0d708cd61a
compiler/target: split RISCV target into float/non-float
2021-11-08 16:59:08 +08:00
03b803e764
firmware: adjust csr separation
2021-11-08 16:59:08 +08:00
b3e315e24a
rust: find json file using CARGO_TRIPLE
2021-11-08 16:59:08 +08:00
0898e101e2
board_misoc: reuse riscv dir for comm & kernel
2021-11-08 16:59:08 +08:00
cb247f235f
gateware: pass adr_w/data_w to submodules
2021-11-08 16:59:08 +08:00
90f944481c
kernel_cpu: add fpu if not kasli v1.x
2021-11-08 16:59:08 +08:00
d84ad0095b
comm_cpu: select 64b bus if not kasli v1.x
2021-11-08 16:59:08 +08:00
dd68b4ab82
mailbox: parametrize address width
2021-11-08 16:59:08 +08:00
c6e0e26440
drtio: accept 32b/64b bus
2021-11-08 16:59:08 +08:00
8da924ec0f
dma: set conversion granularity using bus width
2021-11-08 16:59:08 +08:00
e5620a6b7f
language: remove old type annotations
2021-11-03 22:07:44 +08:00
977543e05a
Merge branch 'master' into nac3
2021-11-03 21:37:18 +08:00
591507a7c0
Merge pull request #1774 from m-labs/fastino-cic
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Fastino cic
2021-10-28 17:44:20 +02:00
5a5b0cc7c0
fastino: expand docs
2021-10-28 15:19:48 +00:00
69cddc6b86
rtio_clocking: add warnings for unsupported rtio_clock settings ( #1773 )
2021-10-28 16:34:22 +08:00
9b1d7e297d
runtime: clock input specification improvements
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closes #1735
2021-10-28 16:21:51 +08:00
1ff474893d
Revert "fastino: make driver filter order configurable"
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This reverts commit 10c37b87ec
2021-10-28 06:29:56 +00:00
10c37b87ec
fastino: make driver filter order configurable
2021-10-27 20:24:58 +00:00
c940f104f1
artiq_flash: fix gateware header not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
0aa8a739aa
sayma_rtm: fix RTM firmware not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
d5fa3d131a
cargo.lock: update libc version for libfringe
2021-10-16 17:42:24 +08:00
6d3164a912
riscv: print mtval on panic
2021-10-16 17:42:24 +08:00
46326716fd
runtime: bump libfringe, impl ecall abi
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See libfringe PR: M-Labs/libfringe#1
2021-10-16 17:42:24 +08:00
0a59c889de
satman/kern: init locked PMP on startup
2021-10-16 17:42:24 +08:00
27a7a96626
runtime: setup pmp + transfer to user
2021-10-16 17:42:24 +08:00
a0bf11b465
riscv: impl pmp
2021-10-16 17:42:24 +08:00
790a20edf6
linker: generate stack guard + symbol
2021-10-16 17:42:24 +08:00
fanmingyu212
178a86bcda
master: add an argument to set an experiment subdirectory
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Signed-off-by: Mingyu Fan <mingyufan@ucsb.edu>
2021-10-15 16:54:31 +08:00
fbd5c70250
Revert "runtime: expose rint from libm"
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Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6
2021-10-11 08:12:58 +08:00
35d21c98d3
Revert "runtime: expose rint from libm"
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Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6
2021-10-11 08:12:04 +08:00
17c283d091
runtime: expose rint from libm
2021-10-10 20:40:56 +08:00
f5100702f6
runtime: expose rint from libm
2021-10-10 20:40:17 +08:00
3c1cbf47d2
phaser: add more slack during init. Closes #1757
2021-10-10 16:18:55 +08:00
3f6bf33298
fastino: add interpolator support
2021-10-08 15:47:07 +00:00
97909d7619
remove old compiler, add nac3 dependency (WIP)
2021-10-08 00:30:27 +08:00
59065c4663
alloc_list: support alloc w/ large align
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Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
2021-10-07 12:38:03 +08:00
1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path ( #1760 )
2021-10-07 08:19:38 +08:00
a8333053c9
sinara_tester: add device_db and test selection CLI options
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Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-27 17:44:50 +08:00
3ed10221d8
compiler: remove big-endian support. Closes #1590
2021-09-13 13:40:24 +08:00
e8a7a8f41e
compiler: work around idiotic windoze behavior that causes conda ld.lld not to be found
2021-09-13 10:40:54 +08:00
ffb1e3ec2d
wavesynth: np.int is deprecated
2021-09-13 07:02:35 +08:00
2d79d824f9
firmware: remove minor or1k leftovers
2021-09-12 20:03:37 +08:00
a573dcf3f9
board_misoc/build: use rv32 as target arg
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The original rv64 argument was only to match the misoc counterpart.
2021-09-10 14:11:23 +08:00
448974fe11
runtime/main: cleanup
2021-09-10 13:59:53 +08:00
b091d8cb66
kernel: flush cache before mod_init
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This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
2021-09-10 13:25:12 +08:00
5394d04669
test_spi: add delay
2021-09-10 13:25:12 +08:00
b8ed5a0d91
alloc: fix alignment for riscv32 arch
2021-09-10 13:25:12 +08:00
2213e7ffac
ksupp/rtio/exception: fix timestamp
2021-09-10 13:25:12 +08:00
09ffd9de1e
dma: fix timestamp fetch
2021-09-10 13:25:12 +08:00
051a14abf2
rtio/dma: fix endianness
2021-09-10 13:25:12 +08:00
c6ba0f3cf4
ksupport: fix dma cslice (ffi)
2021-09-10 13:25:12 +08:00
c812a837ab
runtime: enlarge stack size
2021-09-10 13:25:12 +08:00
a596db404d
satman: fix cargo xbuild sysroot
2021-09-10 13:25:12 +08:00
4fab267593
cargo: std dependency hack
2021-09-10 13:25:12 +08:00
dcbd9f905c
cargo: use cargo xbuild
2021-09-10 13:25:12 +08:00
9f6b3f6014
firmware: clarify target triple
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The lack of compressed instruction support can be inferred from the target triple, literally.
2021-09-10 13:25:12 +08:00
4619a33db4
test: remove broken array return tests
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Removed test cases that do not respect lifetime/scope constraint.
See discussion in artiq-zynq repo: M-Labs/artiq-zynq#119
Referred to the patch from @dnadlinger. 5faa30a837
2021-09-10 13:25:12 +08:00
5985f7efb5
syscall: lower nowrite to inaccessiblememonly
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In the origin implementation, the `nowrite` flag literally means not writing memory at all.
Due to the usage of flags on certain functions, it results in the same issues found in artiq-zynq after optimization passes. (M-Labs/artiq-zynq#119 )
A fix wrote by @dnadlinger can resolve this issue. (c1e46cc7c8
2021-09-10 13:25:12 +08:00
6db7280b09
flake: board package WIP
2021-09-10 13:25:12 +08:00
d8ac429059
dyld: streamline lib.rs
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Only riscv32 is supported anyway, no need to have excessive architecture check.
2021-09-10 13:25:12 +08:00
798774192d
slave_fpga/bootloader: read in little endian
2021-09-10 13:25:12 +08:00
eecd825d23
firmware: suppress warning
2021-09-10 13:25:12 +08:00
