artiq/artiq/coredevice/__init__.py

from artiq.coredevice import exceptions, dds, spi
from artiq.coredevice.exceptions import (RTIOUnderflow, RTIOSequenceError,
                                         RTIOCollisionError, RTIOOverflow,
                                         DDSBatchError, CacheError)
from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE,
                                  PHASE_MODE_TRACKING)

__all__ = []
__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollisionError",
            "RTIOOverflow", "DDSBatchError", "CacheError"]
__all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE",
            "PHASE_MODE_TRACKING"]
runtime/rtio: fix rtio_input_wait(), add RTIOTimeout 2016-03-01 02:49:15 +08:00			`from artiq.coredevice import exceptions, dds, spi`
artiq.experiment: merge language and coredevice namespaces perl -i -pe 's/^from artiq import \$/from artiq.experiment import /' your_experiments/*.py (assuming you skipped the changes form the previous commit) 2016-01-26 06:49:08 +08:00			`from artiq.coredevice.exceptions import (RTIOUnderflow, RTIOSequenceError,`
coredevice: re-export more exceptions. 2016-02-24 21:48:05 +08:00			`RTIOCollisionError, RTIOOverflow,`
rt2wb, exceptions: remove RTIOTimeout Assume that rt2wb transactions either collide and are then reported (https://github.com/m-labs/artiq/issues/308) or that they complete and the delay with which they complete does not matter. If a transaction is ack'ed with a delay because the WB core's downstream logic is busy, that may lead to a later collision with another WB transaction. 2016-03-01 21:44:07 +08:00			`DDSBatchError, CacheError)`
artiq.experiment: merge language and coredevice namespaces perl -i -pe 's/^from artiq import \$/from artiq.experiment import /' your_experiments/*.py (assuming you skipped the changes form the previous commit) 2016-01-26 06:49:08 +08:00			`from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE,`
			`PHASE_MODE_TRACKING)`

			`__all__ = []`
coredevice: re-export more exceptions. 2016-02-24 21:48:05 +08:00			`__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollisionError",`
rt2wb, exceptions: remove RTIOTimeout Assume that rt2wb transactions either collide and are then reported (https://github.com/m-labs/artiq/issues/308) or that they complete and the delay with which they complete does not matter. If a transaction is ack'ed with a delay because the WB core's downstream logic is busy, that may lead to a later collision with another WB transaction. 2016-03-01 21:44:07 +08:00			`"RTIOOverflow", "DDSBatchError", "CacheError"]`
artiq.experiment: merge language and coredevice namespaces perl -i -pe 's/^from artiq import \$/from artiq.experiment import /' your_experiments/*.py (assuming you skipped the changes form the previous commit) 2016-01-26 06:49:08 +08:00			`__all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE",`
			`"PHASE_MODE_TRACKING"]`