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forked from M-Labs/artiq
artiq/artiq/coredevice
Robert Jordens f754d2c117 Merge branch 'spimaster'
* spimaster: (52 commits)
  runtime/rtio: rtio_process_exceptional_status() has only one user
  coredevice.spi, doc/manual: add spi
  kc705: move ttl channels together again, update doc
  runtime: rt2wb_input -> rtio_input_data
  examples/tdr: adapt to compiler changes
  bridge: really fix O/OE
  runtime: define constants for ttl addresses
  coredevice.ttl: fix sensitivity
  bridge: fix ttl o/oe addresses
  runtime: refactor ttl*()
  rtio: rm rtio_write_and_process_status
  coredevice.spi: unused import
  rt2wb, exceptions: remove RTIOTimeout
  gateware.spi: delay only writes to data register, update doc
  nist_clock: disable spi1/2
  runtime/rt2wb: use input/output terminology and add (async) input
  examples: update device_db for nist_clock spi
  gateware.spi: rework wb bus sequence
  nist_clock: rename spi*.ce to spi*.cs_n
  nist_clock: add SPIMasters to spi buses
  ...
2016-03-01 22:08:08 +01:00
..
__init__.py rt2wb, exceptions: remove RTIOTimeout 2016-03-01 14:44:07 +01:00
analyzer.py Commit missing parts of 1465fe6f8. 2016-02-15 21:42:51 +00:00
comm_dummy.py compiler.embedding: instantiate RPC method types (fixes #180). 2015-11-27 16:29:13 +08:00
comm_generic.py coredevice: do not give up on UTF-8 errors in log. Closes #300 2016-02-29 22:21:10 +08:00
comm_tcp.py coredevice/comm_tcp: support retrieving analyzer data 2015-12-18 18:22:50 +08:00
core.py compiler: only use colors in diagnostics on POSIX (fixes #272). 2016-02-22 11:27:45 +00:00
dds.py coredevice/dds: use explicit 64-bit ints for ftw computations 2016-01-14 15:25:01 -07:00
exceptions.py rt2wb, exceptions: remove RTIOTimeout 2016-03-01 14:44:07 +01:00
rtio.py runtime: rt2wb_input -> rtio_input_data 2016-03-01 19:22:42 +01:00
runtime.py artiq_dir: move out of tools to unlink dependencies 2016-01-25 18:15:50 -07:00
spi.py coredevice.spi, doc/manual: add spi 2016-03-01 21:29:09 +01:00
ttl.py Merge branch 'spimaster' 2016-03-01 22:08:08 +01:00