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c6fa18344e
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uncached: disable cachable/bufferable
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2020-06-26 22:32:49 +02:00 |
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5c69bbdad6
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mmu: fix L1Table.update() flush
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2020-06-26 22:31:56 +02:00 |
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d96343c249
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uncached: refactor into UncachedSlice
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2020-06-18 01:28:25 +02:00 |
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ae739146c5
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cache: add the required barriers
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2020-06-18 01:27:34 +02:00 |
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f50018092c
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mmu: add early memory barrier to L1Table.update()
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2020-06-18 01:27:34 +02:00 |
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7c4d390ce4
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libcortex_a9: start Uncached
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2020-06-18 01:27:34 +02:00 |
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6761575b30
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mmu: add L1Table.update()
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2020-06-18 01:27:34 +02:00 |
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aebce435e2
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mmu: switch bufferable=1 (writeback) for DDR pages
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2020-06-18 01:27:34 +02:00 |
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5332587de6
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Changed mutability
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2020-06-10 12:54:50 +08:00 |
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66cd0c7630
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libcortex_a9: allow access for full 1GB of DDR
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2020-05-09 02:35:39 +02:00 |
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0d4d021b1b
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clean up
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2020-05-01 01:17:53 +02:00 |
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2c756ba32e
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libcortex_a9: migrate from asm! to llvm_asm! to avoid future breakage
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2020-05-01 01:11:35 +02:00 |
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008a995429
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libcortex_a9: remove mmu::l1_table alignment through linker script
no longer needed, #[repr(16384)] works now
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2020-04-30 03:38:27 +02:00 |
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282b4dc69a
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link.x: reduce alignment, use all remaining OCM for .stack
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2020-04-28 02:50:07 +02:00 |
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614b1ef350
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regs: add MVBAR and HVBAR
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2020-04-27 12:49:18 +08:00 |
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fefd2a4ceb
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regs: add VBAR
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2020-04-27 12:34:15 +08:00 |
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b26327e474
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typo
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2020-04-13 10:39:38 +08:00 |
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0000575ce0
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libasync: add async_send/async_recv methods
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2020-04-13 01:24:37 +02:00 |
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6fd6f429fe
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libcortex_a9: impl Iterator for sync_channel::Receiver
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2020-04-09 02:56:54 +02:00 |
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e54edbf32d
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libcortex_a9: add sync_channel
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2020-04-09 02:49:24 +02:00 |
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64771bf233
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libcortex_a9: revamp cache maintenance
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2020-04-09 00:18:23 +02:00 |
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965a00801e
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libcortex_a9: set DDR pages non-bufferable to fix eth dma
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2020-03-31 01:09:28 +02:00 |
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1e5fe1b836
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regs: add more #[inline] annotations
reduces .text size by 740 bytes
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2020-02-03 00:50:13 +01:00 |
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cf1983e543
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split into lib{register, cortex_a9, board_zynq, board_zc706} crates
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2019-12-17 23:35:58 +01:00 |
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