20 Commits

Author	SHA1	Message	Date
Astro	2d1c8e1f4f	zynq::flash: fix txd[123] alignment	2019-12-14 01:07:15 +01:00
Astro	e1068af948	zynq::flash: add rdsr1()	2019-12-12 01:02:09 +01:00
Astro	3b3b5dc7c1	zynq::flash: add support for writing 1/2/3-byte words	2019-12-12 00:17:34 +01:00
Astro	70d56d2b28	zynq::flash: doc	2019-12-12 00:13:02 +01:00
Astro	b346ea8297	zynq::flash: fix INST_RDCR	2019-12-12 00:11:42 +01:00
Astro	e9b80eaef9	zynq::flash: don't send excess data, fixes, refactorings	2019-12-10 02:50:44 +01:00
Astro	0823a74164	zynq::flash: fix rx_thres register	2019-12-10 02:46:25 +01:00
Astro	aab82f6843	zynq::flash: enable big endian mode	2019-12-10 02:45:05 +01:00
Astro	f3676c945a	zynq::flash: flush after instruction	2019-12-07 02:48:55 +01:00
Astro	1e465250f5	zynq::flash: enable/disable spi for every transfer	2019-12-07 02:11:50 +01:00
Astro	e37659e4b3	zynq::flash: refactor	2019-12-05 01:18:52 +01:00
Astro	45cc271735	zynq::flash: fix + refactor	2019-12-05 00:05:34 +01:00
Astro	cfaa1213e2	zynq::flash: add more initialization	2019-12-03 02:41:49 +01:00
Astro	7107244a6e	zynq::flash: start implementing Manual mode	2019-11-30 02:48:39 +01:00
Astro	dd3ad3be67	zynq::flash: implement stopping LinearAddressing mode	2019-11-29 23:48:08 +01:00
Astro	a8a7f11990	zynq::flash: configure quad i/o fast read mode	2019-11-29 23:37:54 +01:00
Astro	78caca1f04	zynq::flash: setup additional signals	2019-11-28 03:22:26 +01:00
Astro	5642feb824	zynq::flash: add missing config bits to enable addressing mode	2019-11-28 03:02:51 +01:00
Astro	a199a5dc7d	zynq::flash: add more setup	2019-11-23 01:59:24 +01:00
Astro	3180f1c3f7	zynq::flash: begin driver implementation	2019-11-21 00:14:09 +01:00