forked from M-Labs/zynq-rs
remove flash support
PITA to get to work and most boards have SD.
This commit is contained in:
parent
a6955edf14
commit
e601ac9c45
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@ -15,7 +15,7 @@ use libboard_zynq::{
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self as zynq,
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clocks::source::{ArmPll, ClockSource, IoPll},
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clocks::Clocks,
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print, println, stdio,
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println, stdio,
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mpcore,
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gic,
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smoltcp::{
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@ -140,17 +140,6 @@ pub fn main_core0() {
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clocks.cpu_1x()
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);
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let mut flash = zynq::flash::Flash::flash(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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for i in 0..=1 {
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print!("Flash {}:", i);
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for b in &flash_ram[(i * 16 * 1024 * 1024)..][..128] {
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print!(" {:02X}", *b);
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}
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println!("");
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}
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let _flash = flash.stop();
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let timer = libboard_zynq::timer::GlobalTimer::start();
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let mut ddr = zynq::ddr::DdrRam::ddrram();
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@ -158,45 +147,6 @@ pub fn main_core0() {
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ddr.memtest();
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ram::init_alloc_ddr(&mut ddr);
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#[cfg(dev)]
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for i in 0..=1 {
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let mut flash_io = flash.manual_mode(i);
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// println!("rdcr={:02X}", flash_io.rdcr());
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print!("Flash {} ID:", i);
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for b in flash_io.rdid() {
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print!(" {:02X}", b);
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}
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println!("");
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print!("Flash {} I/O:", i);
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for o in 0..8 {
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const CHUNK: u32 = 8;
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for b in flash_io.read(CHUNK * o, CHUNK as usize) {
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print!(" {:02X}", b);
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}
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}
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println!("");
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flash_io.dump("Read cr1", 0x35);
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flash_io.dump("Read Autoboot", 0x14);
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flash_io.dump("Read Bank", 0x16);
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flash_io.dump("DLP Bank", 0x16);
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flash_io.dump("Read ESig", 0xAB);
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flash_io.dump("OTP Read", 0x4B);
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flash_io.dump("DYB Read", 0xE0);
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flash_io.dump("PPB Read", 0xE2);
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flash_io.dump("ASP Read", 0x2B);
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flash_io.dump("Password Read", 0xE7);
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flash_io.write_enabled(|flash_io| {
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flash_io.erase(0);
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});
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flash_io.write_enabled(|flash_io| {
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flash_io.program(0, [0x23054223; 0x100 >> 2].iter().cloned());
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});
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flash = flash_io.stop();
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}
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boot::Core1::start(false);
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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@ -1,41 +0,0 @@
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pub trait BytesTransferExt: Sized {
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// Turn u32 into u8
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fn bytes_transfer(self) -> BytesTransfer<Self>
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where
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Self: Iterator<Item = u32>;
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}
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impl<I: Iterator<Item = u32>> BytesTransferExt for I {
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// Turn u32 into u8
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fn bytes_transfer(self) -> BytesTransfer<Self> {
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BytesTransfer {
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iter: self,
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shift: 0,
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word: 0,
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}
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}
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}
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pub struct BytesTransfer<I: Iterator<Item = u32> + Sized> {
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iter: I,
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shift: u8,
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word: u32,
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}
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impl<I: Iterator<Item = u32> + Sized> Iterator for BytesTransfer<I> {
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type Item = u8;
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fn next(&mut self) -> Option<u8> {
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if self.shift > 0 {
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self.shift -= 8;
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Some((self.word >> self.shift) as u8)
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} else {
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self.iter.next()
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.and_then(|word| {
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self.shift = 32;
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self.word = word;
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self.next()
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})
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}
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}
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}
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@ -1,503 +0,0 @@
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//! Quad-SPI Flash Controller
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use core::marker::PhantomData;
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use log::{error, info, warn};
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use crate::{print, println};
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use super::slcr;
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use super::clocks::source::{IoPll, ClockSource};
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mod regs;
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mod bytes;
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pub use bytes::{BytesTransferExt, BytesTransfer};
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mod spi_flash_register;
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use spi_flash_register::*;
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mod transfer;
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use transfer::Transfer;
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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/// 16 MB
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pub const SINGLE_CAPACITY: u32 = 0x1000000;
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pub const SECTOR_SIZE: u32 = 0x10000;
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pub const PAGE_SIZE: u32 = 0x100;
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/// Instruction: Read Identification
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const INST_RDID: u8 = 0x9F;
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/// Instruction: Read
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const INST_READ: u8 = 0x03;
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/// Instruction: Quad I/O Fast Read
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const INST_4IO_FAST_READ: u8 = 0xEB;
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/// Instruction: Write Disable
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const INST_WRDI: u8 = 0x04;
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/// Instruction: Write Enable
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const INST_WREN: u8 = 0x06;
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/// Instruction: Program page
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const INST_PP: u8 = 0x02;
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/// Instruction: Erase 4K Block
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const INST_BE_4K: u8 = 0x20;
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#[derive(Clone)]
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pub enum SpiWord {
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W8(u8),
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W16(u16),
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W24(u32),
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W32(u32),
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}
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impl From<u8> for SpiWord {
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fn from(x: u8) -> Self {
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SpiWord::W8(x)
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}
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}
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impl From<u16> for SpiWord {
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fn from(x: u16) -> Self {
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SpiWord::W16(x)
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}
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}
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impl From<u32> for SpiWord {
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fn from(x: u32) -> Self {
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SpiWord::W32(x)
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}
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}
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/// Memory-mapped mode
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pub struct LinearAddressing;
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/// Manual I/O mode
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pub struct Manual;
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/// Flash Interface Driver
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///
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/// For 2x Spansion S25FL128SAGMFIR01
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pub struct Flash<MODE> {
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regs: &'static mut regs::RegisterBlock,
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_mode: PhantomData<MODE>,
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}
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impl<MODE> Flash<MODE> {
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fn transition<TO>(self) -> Flash<TO> {
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Flash {
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regs: self.regs,
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_mode: PhantomData,
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}
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}
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fn disable_interrupts(&mut self) {
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.rx_overflow(true)
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.tx_fifo_not_full(true)
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.tx_fifo_full(true)
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.rx_fifo_not_empty(true)
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.rx_fifo_full(true)
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.tx_fifo_underflow(true)
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);
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}
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fn clear_rx_fifo(&self) {
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while self.regs.intr_status.read().rx_fifo_not_empty() {
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let _ = self.regs.rx_data.read();
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}
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}
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fn clear_interrupt_status(&mut self) {
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self.regs.intr_status.write(
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regs::IntrStatus::zeroed()
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.rx_overflow(true)
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.tx_fifo_underflow(true)
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);
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}
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fn wait_tx_fifo_flush(&mut self) {
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self.regs.config.modify(|_, w| w.man_start_com(true));
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while !self.regs.intr_status.read().tx_fifo_not_full() {}
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}
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}
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impl Flash<()> {
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pub fn flash(clock: u32) -> Self {
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Self::enable_clocks(clock);
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Self::setup_signals();
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Self::reset();
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let regs = regs::RegisterBlock::qspi();
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let mut flash = Flash { regs, _mode: PhantomData };
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flash.configure((FLASH_BAUD_RATE - 1 + clock) / FLASH_BAUD_RATE);
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flash
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}
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/// typical: `200_000_000` Hz
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fn enable_clocks(clock: u32) {
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let io_pll = IoPll::freq();
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let divisor = ((clock - 1 + io_pll) / clock)
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.max(1).min(63) as u8;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.lqspi_clk_ctrl.write(
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slcr::LqspiClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor(divisor)
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.clkact(true)
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);
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});
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}
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fn setup_signals() {
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slcr::RegisterBlock::unlocked(|slcr| {
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// 1. Configure MIO pin 1 for chip select 0 output.
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slcr.mio_pin_01.write(
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slcr::MioPin01::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// Configure MIO pins 2 through 5 for I/O.
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slcr.mio_pin_02.write(
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slcr::MioPin02::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_03.write(
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slcr::MioPin03::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_04.write(
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slcr::MioPin04::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_05.write(
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slcr::MioPin05::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// 3. Configure MIO pin 6 for serial clock 0 output.
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slcr.mio_pin_06.write(
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slcr::MioPin06::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// Option: Add Second Device Chip Select
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// 4. Configure MIO pin 0 for chip select 1 output.
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slcr.mio_pin_00.write(
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slcr::MioPin00::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// Option: Add Second Serial Clock
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// 5. Configure MIO pin 9 for serial clock 1 output.
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slcr.mio_pin_09.write(
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slcr::MioPin09::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// Option: Add 4-bit Data
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// 6. Configure MIO pins 10 through 13 for I/O.
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slcr.mio_pin_10.write(
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slcr::MioPin10::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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slcr.mio_pin_11.write(
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slcr::MioPin11::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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slcr.mio_pin_12.write(
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slcr::MioPin12::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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slcr.mio_pin_13.write(
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slcr::MioPin13::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// Option: Add Feedback Output Clock
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// 7. Configure MIO pin 8 for feedback clock.
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slcr.mio_pin_08.write(
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slcr::MioPin08::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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});
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}
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fn reset() {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.lqspi_rst_ctrl.write(
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slcr::LqspiRstCtrl::zeroed()
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.ref_rst(true)
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.cpu1x_rst(true)
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);
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slcr.lqspi_rst_ctrl.write(
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slcr::LqspiRstCtrl::zeroed()
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);
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});
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}
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fn configure(&mut self, divider: u32) {
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// Disable
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self.regs.enable.write(
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regs::Enable::zeroed()
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);
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self.disable_interrupts();
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self.regs.lqspi_cfg.write(
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regs::LqspiCfg::zeroed()
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);
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self.clear_rx_fifo();
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self.clear_interrupt_status();
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// for a baud_rate_div=1 LPBK_DLY_ADJ would be required
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let mut baud_rate_div = 2u32;
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while baud_rate_div < 7 && 2u32.pow(1 + baud_rate_div) < divider {
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baud_rate_div += 1;
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}
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self.regs.config.write(regs::Config::zeroed()
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.baud_rate_div(baud_rate_div as u8)
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.mode_sel(true)
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.leg_flsh(true)
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.holdb_dr(true)
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// 32 bits TX FIFO width
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.fifo_width(0b11)
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);
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// Initialize RX/TX pipes thresholds
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unsafe {
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self.regs.rx_thres.write(1);
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self.regs.tx_thres.write(1);
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}
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}
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pub fn linear_addressing_mode(self) -> Flash<LinearAddressing> {
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// Set manual start enable to auto mode.
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// Assert the chip select.
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self.regs.config.modify(|_, w| w
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.man_start_en(false)
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.pcs(false)
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.manual_cs(false)
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);
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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// Quad I/O Fast Read
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.inst_code(INST_4IO_FAST_READ)
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.dummy_mask(0x2)
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.mode_en(false)
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.mode_bits(0xFF)
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// 2 devices
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.two_mem(true)
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.u_page(false)
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// Quad SPI mode
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.lq_mode(true)
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);
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self.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(true)
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);
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self.transition()
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}
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pub fn manual_mode(self, chip_index: usize) -> Flash<Manual> {
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self.regs.config.modify(|_, w| w
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.man_start_en(true)
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.manual_cs(true)
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.endian(true)
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);
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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// Quad I/O Fast Read
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.inst_code(INST_READ)
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.dummy_mask(0x2)
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.mode_en(false)
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.mode_bits(0xFF)
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// 2 devices
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.two_mem(true)
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.u_page(chip_index != 0)
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// Quad SPI mode
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.lq_mode(false)
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);
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self.transition()
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}
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}
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impl Flash<LinearAddressing> {
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/// Stop linear addressing mode
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pub fn stop(self) -> Flash<()> {
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self.regs.enable.modify(|_, w| w.spi_en(false));
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// De-assert chip select.
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self.regs.config.modify(|_, w| w.pcs(true));
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self.transition()
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}
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pub fn ptr<T>(&mut self) -> *mut T {
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0xFC00_0000 as *mut _
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}
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pub fn size(&self) -> usize {
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2 * (SINGLE_CAPACITY as usize)
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}
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}
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impl Flash<Manual> {
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pub fn stop(self) -> Flash<()> {
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self.transition()
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}
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pub fn read_reg<R: SpiFlashRegister>(&mut self) -> R {
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let args = Some(R::inst_code());
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let transfer = self.transfer(args.into_iter(), 2)
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.bytes_transfer();
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R::new(transfer.skip(1).next().unwrap())
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}
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pub fn read_reg_until<R, F, A>(&mut self, f: F) -> A
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where
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R: SpiFlashRegister,
|
||||
F: Fn(R) -> Option<A>,
|
||||
{
|
||||
let mut result = None;
|
||||
while result.is_none() {
|
||||
let args = Some(R::inst_code());
|
||||
for b in self.transfer(args.into_iter(), 32)
|
||||
.bytes_transfer().skip(1) {
|
||||
result = f(R::new(b));
|
||||
|
||||
if result.is_none() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
result.unwrap()
|
||||
}
|
||||
|
||||
/// Status Register-1 remains `0x00` immediately after invoking a command.
|
||||
fn wait_while_sr1_zeroed(&mut self) -> SR1 {
|
||||
self.read_reg_until::<SR1, _, SR1>(|sr1|
|
||||
if sr1.is_zeroed() {
|
||||
None
|
||||
} else {
|
||||
Some(sr1)
|
||||
}
|
||||
)
|
||||
}
|
||||
|
||||
/// Read Identification
|
||||
pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>> {
|
||||
let args = Some((INST_RDID as u32) << 24);
|
||||
self.transfer(args.into_iter(), 0x44)
|
||||
.bytes_transfer().skip(1)
|
||||
}
|
||||
|
||||
/// Read flash data
|
||||
pub fn read(&mut self, offset: u32, len: usize
|
||||
) -> core::iter::Take<core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>>>
|
||||
{
|
||||
let args = Some(((INST_READ as u32) << 24) | (offset as u32));
|
||||
self.transfer(args.into_iter(), len + 6)
|
||||
.bytes_transfer().skip(6).take(len)
|
||||
}
|
||||
|
||||
pub fn erase(&mut self, offset: u32) {
|
||||
let args = Some(((INST_BE_4K as u32) << 24) | (offset as u32));
|
||||
self.transfer(args.into_iter(), 4);
|
||||
|
||||
let sr1 = self.wait_while_sr1_zeroed();
|
||||
|
||||
if sr1.e_err() {
|
||||
error!("E_ERR");
|
||||
} else if sr1.p_err() {
|
||||
error!("P_ERR");
|
||||
} else if sr1.wip() {
|
||||
info!("Erase in progress");
|
||||
while self.read_reg::<SR1>().wip() {
|
||||
print!(".");
|
||||
}
|
||||
println!("");
|
||||
} else {
|
||||
warn!("erased? sr1={:02X}", sr1.inner);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn program<I: Iterator<Item=u32>>(&mut self, offset: u32, data: I) {
|
||||
{
|
||||
let len = 4 + 4 * data.size_hint().0;
|
||||
let args = Some(SpiWord::W32(((INST_PP as u32) << 24) | (offset as u32))).into_iter()
|
||||
.chain(data.map(SpiWord::W32));
|
||||
self.transfer(args, len);
|
||||
}
|
||||
|
||||
// let sr1 = self.wait_while_sr1_zeroed();
|
||||
let sr1 = self.read_reg::<SR1>();
|
||||
|
||||
if sr1.e_err() {
|
||||
error!("E_ERR");
|
||||
} else if sr1.p_err() {
|
||||
error!("P_ERR");
|
||||
} else if sr1.wip() {
|
||||
info!("Program in progress");
|
||||
while self.read_reg::<SR1>().wip() {
|
||||
print!(".");
|
||||
}
|
||||
println!("");
|
||||
} else {
|
||||
warn!("programmed? sr1={:02X}", sr1.inner);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn write_enabled<F: Fn(&mut Self) -> R, R>(&mut self, f: F) -> R {
|
||||
// Write Enable
|
||||
let args = Some(INST_WREN);
|
||||
self.transfer(args.into_iter(), 1);
|
||||
self.regs.gpio.modify(|_, w| w.wp_n(true));
|
||||
let sr1 = self.wait_while_sr1_zeroed();
|
||||
if !sr1.wel() {
|
||||
panic!("Cannot write-enable flash");
|
||||
}
|
||||
|
||||
let result = f(self);
|
||||
|
||||
// Write Disable
|
||||
let args = Some(INST_WRDI);
|
||||
self.transfer(args.into_iter(), 1);
|
||||
self.regs.gpio.modify(|_, w| w.wp_n(false));
|
||||
|
||||
result
|
||||
}
|
||||
|
||||
pub fn transfer<'s: 't, 't, Args, W>(&'s mut self, args: Args, len: usize) -> Transfer<'t, Args, W>
|
||||
where
|
||||
Args: Iterator<Item = W>,
|
||||
W: Into<SpiWord>,
|
||||
{
|
||||
Transfer::new(self, args, len)
|
||||
}
|
||||
|
||||
pub fn dump(&mut self, label: &'_ str, inst_code: u8) {
|
||||
print!("{}:", label);
|
||||
|
||||
let args = Some(u32::from(inst_code) << 24);
|
||||
for b in self.transfer(args.into_iter(), 32).bytes_transfer() {
|
||||
print!(" {:02X}", b);
|
||||
}
|
||||
println!("");
|
||||
}
|
||||
}
|
|
@ -1,122 +0,0 @@
|
|||
use volatile_register::{RO, WO, RW};
|
||||
|
||||
use libregister::{register, register_at, register_bit, register_bits};
|
||||
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
pub config: Config,
|
||||
pub intr_status: IntrStatus,
|
||||
pub intr_en: IntrEn,
|
||||
pub intr_dis: IntrDis,
|
||||
pub intr_mask: RO<u32>,
|
||||
pub enable: Enable,
|
||||
pub delay: RW<u32>,
|
||||
pub txd0: WO<u32>,
|
||||
pub rx_data: RO<u32>,
|
||||
pub slave_idle_count: RW<u32>,
|
||||
pub tx_thres: RW<u32>,
|
||||
pub rx_thres: RW<u32>,
|
||||
pub gpio: QspiGpio,
|
||||
pub _unused1: RO<u32>,
|
||||
pub lpbk_dly_adj: RW<u32>,
|
||||
pub _unused2: [RO<u32>; 17],
|
||||
pub txd1: WO<u32>,
|
||||
pub txd2: WO<u32>,
|
||||
pub txd3: WO<u32>,
|
||||
pub _unused3: [RO<u32>; 5],
|
||||
pub lqspi_cfg: LqspiCfg,
|
||||
pub lqspi_sts: RW<u32>,
|
||||
pub _unused4: [RO<u32>; 21],
|
||||
pub mod_id: RW<u32>,
|
||||
}
|
||||
|
||||
const BASE_ADDRESS: u32 = 0xE000D000;
|
||||
|
||||
register_at!(RegisterBlock, 0xE000D000, qspi);
|
||||
|
||||
register!(config, Config, RW, u32);
|
||||
register_bit!(config,
|
||||
/// Enables master mode
|
||||
mode_sel, 0);
|
||||
register_bit!(config,
|
||||
/// Clock polarity low/high
|
||||
clk_pol, 1);
|
||||
register_bit!(config,
|
||||
/// Clock phase
|
||||
clk_ph, 2);
|
||||
register_bits!(config,
|
||||
/// divider = 2 ** (1 + baud_rate_div)
|
||||
baud_rate_div, u8, 3, 5);
|
||||
register_bits!(config,
|
||||
/// Must be set to 0b11
|
||||
fifo_width, u8, 6, 7);
|
||||
register_bit!(config,
|
||||
/// Must be 0
|
||||
ref_clk, 8);
|
||||
register_bit!(config,
|
||||
/// Peripheral Chip Select Line
|
||||
pcs, 10);
|
||||
register_bit!(config,
|
||||
/// false: auto mode, true: manual CS mode
|
||||
manual_cs, 14);
|
||||
register_bit!(config,
|
||||
/// false: auto mode, true: enables manual start enable
|
||||
man_start_en, 15);
|
||||
register_bit!(config,
|
||||
/// false: auto mode, true: enables manual start command
|
||||
man_start_com, 16);
|
||||
register_bit!(config, holdb_dr, 19);
|
||||
register_bit!(config,
|
||||
/// false: little, true: endian
|
||||
endian, 26);
|
||||
register_bit!(config,
|
||||
/// false: legacy SPI mode, true: Flash memory interface mode
|
||||
leg_flsh, 31);
|
||||
|
||||
register!(intr_status, IntrStatus, RW, u32);
|
||||
register_bit!(intr_status, rx_overflow, 0);
|
||||
register_bit!(intr_status,
|
||||
/// < tx_thres
|
||||
tx_fifo_not_full, 2);
|
||||
register_bit!(intr_status, tx_fifo_full, 3);
|
||||
register_bit!(intr_status,
|
||||
/// >= rx_thres
|
||||
rx_fifo_not_empty, 4);
|
||||
register_bit!(intr_status, rx_fifo_full, 5);
|
||||
register_bit!(intr_status, tx_fifo_underflow, 6);
|
||||
|
||||
register!(intr_en, IntrEn, WO, u32);
|
||||
register_bit!(intr_en, rx_overflow, 0);
|
||||
register_bit!(intr_en, tx_fifo_not_full, 2);
|
||||
register_bit!(intr_en, tx_fifo_full, 3);
|
||||
register_bit!(intr_en, rx_fifo_not_empty, 4);
|
||||
register_bit!(intr_en, rx_fifo_full, 5);
|
||||
register_bit!(intr_en, tx_fifo_underflow, 6);
|
||||
|
||||
register!(intr_dis, IntrDis, WO, u32);
|
||||
register_bit!(intr_dis, rx_overflow, 0);
|
||||
register_bit!(intr_dis, tx_fifo_not_full, 2);
|
||||
register_bit!(intr_dis, tx_fifo_full, 3);
|
||||
register_bit!(intr_dis, rx_fifo_not_empty, 4);
|
||||
register_bit!(intr_dis, rx_fifo_full, 5);
|
||||
register_bit!(intr_dis, tx_fifo_underflow, 6);
|
||||
|
||||
register!(enable, Enable, RW, u32);
|
||||
register_bit!(enable, spi_en, 0);
|
||||
|
||||
// named to avoid confusion with normal gpio
|
||||
register!(qspi_gpio, QspiGpio, RW, u32);
|
||||
register_bit!(qspi_gpio,
|
||||
/// Write protect pin (inverted)
|
||||
wp_n, 0);
|
||||
|
||||
register!(lqspi_cfg, LqspiCfg, RW, u32);
|
||||
register_bits!(lqspi_cfg, inst_code, u8, 0, 7);
|
||||
register_bits!(lqspi_cfg, dummy_mask, u8, 8, 10);
|
||||
register_bits!(lqspi_cfg, mode_bits, u8, 16, 23);
|
||||
register_bit!(lqspi_cfg, mode_on, 24);
|
||||
register_bit!(lqspi_cfg, mode_en, 25);
|
||||
register_bit!(lqspi_cfg, u_page, 28);
|
||||
register_bit!(lqspi_cfg, sep_bus, 29);
|
||||
register_bit!(lqspi_cfg, two_mem, 30);
|
||||
register_bit!(lqspi_cfg, lq_mode, 31);
|
|
@ -1,62 +0,0 @@
|
|||
use bit_field::BitField;
|
||||
|
||||
pub trait SpiFlashRegister {
|
||||
fn inst_code() -> u8;
|
||||
fn new(src: u8) -> Self;
|
||||
}
|
||||
|
||||
macro_rules! u8_register {
|
||||
($name: ident, $doc: tt, $inst_code: expr) => {
|
||||
#[derive(Clone)]
|
||||
#[doc=$doc]
|
||||
pub struct $name {
|
||||
pub inner: u8,
|
||||
}
|
||||
|
||||
impl SpiFlashRegister for $name {
|
||||
fn inst_code() -> u8 {
|
||||
$inst_code
|
||||
}
|
||||
|
||||
fn new(src: u8) -> Self {
|
||||
$name {
|
||||
inner: src,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl $name {
|
||||
#[allow(unused)]
|
||||
pub fn is_zeroed(&self) -> bool {
|
||||
self.inner == 0
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
u8_register!(CR, "Configuration Register", 0x35);
|
||||
u8_register!(SR1, "Status Register-1", 0x05);
|
||||
impl SR1 {
|
||||
/// Write In Progress
|
||||
pub fn wip(&self) -> bool {
|
||||
self.inner.get_bit(0)
|
||||
}
|
||||
|
||||
/// Write Enable Latch
|
||||
pub fn wel(&self) -> bool {
|
||||
self.inner.get_bit(1)
|
||||
}
|
||||
|
||||
/// Erase Error Occurred
|
||||
pub fn e_err(&self) -> bool {
|
||||
self.inner.get_bit(5)
|
||||
}
|
||||
|
||||
/// Programming Error Occurred
|
||||
pub fn p_err(&self) -> bool {
|
||||
self.inner.get_bit(6)
|
||||
}
|
||||
}
|
||||
|
||||
u8_register!(SR2, "Status Register-2", 0x07);
|
||||
u8_register!(BA, "Bank Address Register", 0xB9);
|
|
@ -1,125 +0,0 @@
|
|||
use libregister::{RegisterR, RegisterW, RegisterRW};
|
||||
use super::regs;
|
||||
use super::{SpiWord, Flash, Manual};
|
||||
|
||||
pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> {
|
||||
flash: &'a mut Flash<Manual>,
|
||||
args: Args,
|
||||
sent: usize,
|
||||
received: usize,
|
||||
len: usize,
|
||||
}
|
||||
|
||||
impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Transfer<'a, Args, W> {
|
||||
pub fn new(flash: &'a mut Flash<Manual>, args: Args, len: usize) -> Self {
|
||||
flash.regs.config.modify(|_, w| w.pcs(false));
|
||||
flash.regs.enable.write(
|
||||
regs::Enable::zeroed()
|
||||
.spi_en(true)
|
||||
);
|
||||
|
||||
let mut xfer = Transfer {
|
||||
flash,
|
||||
args,
|
||||
sent: 0,
|
||||
received: 0,
|
||||
len,
|
||||
};
|
||||
xfer.fill_tx_fifo();
|
||||
xfer.flash.regs.config.modify(|_, w| w.man_start_com(true));
|
||||
xfer
|
||||
}
|
||||
|
||||
fn fill_tx_fifo(&mut self) {
|
||||
while self.sent < self.len && !self.flash.regs.intr_status.read().tx_fifo_full() {
|
||||
let arg = self.args.next()
|
||||
.map(|n| n.into())
|
||||
.unwrap_or(SpiWord::W32(0));
|
||||
match arg {
|
||||
SpiWord::W32(w) => {
|
||||
// println!("txd0 {:08X}", w);
|
||||
unsafe {
|
||||
self.flash.regs.txd0.write(w);
|
||||
}
|
||||
self.sent += 4;
|
||||
}
|
||||
// Only txd0 can be used without flushing
|
||||
_ => {
|
||||
if !self.flash.regs.intr_status.read().tx_fifo_not_full() {
|
||||
// Flush if necessary
|
||||
self.flash.wait_tx_fifo_flush();
|
||||
}
|
||||
|
||||
match arg {
|
||||
SpiWord::W8(w) => {
|
||||
// println!("txd1 {:02X}", w);
|
||||
unsafe {
|
||||
self.flash.regs.txd1.write(u32::from(w) << 24);
|
||||
}
|
||||
self.sent += 1;
|
||||
}
|
||||
SpiWord::W16(w) => {
|
||||
unsafe {
|
||||
self.flash.regs.txd2.write(u32::from(w) << 16);
|
||||
}
|
||||
self.sent += 2;
|
||||
}
|
||||
SpiWord::W24(w) => {
|
||||
unsafe {
|
||||
self.flash.regs.txd3.write(w << 8);
|
||||
}
|
||||
self.sent += 3;
|
||||
}
|
||||
SpiWord::W32(_) => unreachable!(),
|
||||
}
|
||||
|
||||
self.flash.wait_tx_fifo_flush();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn can_read(&mut self) -> bool {
|
||||
self.flash.regs.intr_status.read().rx_fifo_not_empty()
|
||||
}
|
||||
|
||||
fn read(&mut self) -> u32 {
|
||||
let rx = self.flash.regs.rx_data.read();
|
||||
self.received += 4;
|
||||
rx
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Drop for Transfer<'a, Args, W> {
|
||||
fn drop(&mut self) {
|
||||
// Discard remaining rx_data
|
||||
while self.can_read() {
|
||||
self.read();
|
||||
}
|
||||
|
||||
// Stop
|
||||
self.flash.regs.enable.write(
|
||||
regs::Enable::zeroed()
|
||||
.spi_en(false)
|
||||
);
|
||||
self.flash.regs.config.modify(|_, w| w
|
||||
.pcs(true)
|
||||
.man_start_com(false)
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Iterator for Transfer<'a, Args, W> {
|
||||
type Item = u32;
|
||||
|
||||
fn next<'s>(&'s mut self) -> Option<u32> {
|
||||
if self.received >= self.len {
|
||||
return None;
|
||||
}
|
||||
|
||||
self.fill_tx_fifo();
|
||||
|
||||
while !self.can_read() {}
|
||||
Some(self.read())
|
||||
}
|
||||
}
|
|
@ -16,7 +16,6 @@ pub mod axi_gp;
|
|||
pub mod ddr;
|
||||
pub mod mpcore;
|
||||
pub mod gic;
|
||||
pub mod flash;
|
||||
pub mod time;
|
||||
pub mod timer;
|
||||
pub mod sdio;
|
||||
|
|
Loading…
Reference in New Issue