forked from M-Labs/zynq-rs
devc: add is_done()
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@ -26,12 +26,18 @@ impl DevC {
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})
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}
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pub fn is_done(&self) -> bool {
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// Note: contrary to what the TRM says, this appears to be simply
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// the state of the DONE signal.
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self.regs.int_sts.read().ixr_pcfg_done()
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}
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pub fn program(&mut self) {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.init_preload_fpga();
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});
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while !self.regs.int_sts.read().ixr_pcfg_done() {}
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while !self.is_done() {}
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.init_postload_fpga();
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