forked from M-Labs/zynq-rs
compile fixes
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5a8d714627
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@ -1,5 +1,6 @@
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use crate::regs::*;
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use crate::slcr;
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use crate::println;
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pub mod phy;
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mod regs;
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@ -1,5 +1,6 @@
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use core::ops::{Deref, DerefMut};
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use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
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use crate::println;
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use super::{MTU, regs};
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/// Descriptor entry
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@ -52,7 +53,6 @@ impl<'a> DescList<'a> {
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// every frame contains 1 packet
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.last_buffer(true)
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);
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);
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}
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DescList {
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