forked from M-Labs/zynq-rs
eth: setup_gem0/1_clock()
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5823d90db1
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@ -8,6 +8,7 @@ pub mod tx;
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/// Size of all the buffers
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/// Size of all the buffers
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pub const MTU: usize = 1536;
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pub const MTU: usize = 1536;
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pub const IO_PLL: u32 = 1_000;
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pub struct Eth<RX, TX> {
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pub struct Eth<RX, TX> {
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regs: &'static mut regs::RegisterBlock,
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regs: &'static mut regs::RegisterBlock,
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@ -140,43 +141,14 @@ impl Eth<(), ()> {
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}
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}
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pub fn gem0(macaddr: [u8; 6]) -> Self {
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pub fn gem0(macaddr: [u8; 6]) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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Self::setup_gem0_clock(125);
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slcr.gem0_clk_ctrl.write(
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// 0x0050_0801: 8, 5: 100 Mb/s
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slcr::ClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(8)
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.divisor1(5)
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);
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// Enable gem0 ref clock
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slcr.gem0_rclk_ctrl.write(
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// 0x0000_0801
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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});
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let regs = regs::RegisterBlock::gem0();
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let regs = regs::RegisterBlock::gem0();
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Self::from_regs(regs, macaddr)
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Self::from_regs(regs, macaddr)
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}
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}
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pub fn gem1(macaddr: [u8; 6]) -> Self {
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pub fn gem1(macaddr: [u8; 6]) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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Self::setup_gem1_clock(125);
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slcr.gem1_clk_ctrl.write(
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// 0x0050_0801: 8, 5: 100 Mb/s
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slcr::ClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(8)
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.divisor1(5)
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);
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// Enable gem1 ref clock
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slcr.gem1_rclk_ctrl.write(
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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});
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let regs = regs::RegisterBlock::gem1();
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let regs = regs::RegisterBlock::gem1();
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Self::from_regs(regs, macaddr)
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Self::from_regs(regs, macaddr)
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@ -194,6 +166,50 @@ impl Eth<(), ()> {
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}
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}
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impl<RX, TX> Eth<RX, TX> {
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impl<RX, TX> Eth<RX, TX> {
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pub fn setup_gem0_clock(tx_clock: u32) {
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let d0 = (IO_PLL / tx_clock).min(63);
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let d1 = (IO_PLL / tx_clock / d0).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.gem0_clk_ctrl.write(
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// 0x0050_0801: 8, 5: 100 Mb/s
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// ...: 8, 1: 1000 Mb/s
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slcr::ClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(d0 as u8)
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.divisor1(d1 as u8)
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);
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// Enable gem0 recv clock
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slcr.gem0_rclk_ctrl.write(
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// 0x0000_0801
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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});
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}
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pub fn setup_gem1_clock(tx_clock: u32) {
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let d0 = (IO_PLL / tx_clock).min(63);
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let d1 = (IO_PLL / tx_clock / d0).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.gem1_clk_ctrl.write(
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slcr::ClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(d0 as u8)
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.divisor1(d1 as u8)
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);
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// Enable gem1 recv clock
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slcr.gem1_rclk_ctrl.write(
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// 0x0000_0801
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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});
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}
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fn init(mut self) -> Self {
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fn init(mut self) -> Self {
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// Clear the Network Control register.
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// Clear the Network Control register.
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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