forked from M-Labs/zynq-rs
zynq::ddr: implement reset_ddrc(), add to main
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a8886de067
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@ -94,6 +94,7 @@ fn main() {
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clocks.cpu_3x2x() / 1_000_000,
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clocks.cpu_2x() / 1_000_000,
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clocks.cpu_1x() / 1_000_000);
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let ddr = zynq::ddr::DdrRam::new();
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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@ -2,12 +2,13 @@ use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use super::slcr;
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use super::clocks::CpuClocks;
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mod regs;
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/// Micron MT41J256M8HX-15E: 667 MHz DDR3
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const DDR_FREQ: u32 = 666_666_666;
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const DCI_FREQ: u32 = 10_000_000;
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pub struct DdrRam {
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}
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pub struct DdrRam;
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impl DdrRam {
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pub fn new() -> Self {
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@ -15,9 +16,9 @@ impl DdrRam {
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Self::clock_setup(&clocks);
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Self::calibrate_iob_impedance(&clocks);
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Self::configure_iob();
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Self::reset_ddrc();
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let ram = DdrRam {};
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ram
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DdrRam
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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@ -130,4 +131,17 @@ impl DdrRam {
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);
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});
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}
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/// Reset DDR controller
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fn reset_ddrc() {
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let regs = unsafe { regs::RegisterBlock::new() };
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regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(false)
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);
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regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(true)
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.powerdown_en(false)
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.data_bus_width(regs::DataBusWidth::Width32bit)
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);
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}
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}
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@ -2,9 +2,15 @@ use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_bits_typed};
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#[repr(u8)]
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pub enum DataBusWidth {
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Width32bit = 0b00,
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Width16bit = 0b01,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub ddrc_ctrl: RW<u32>,
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pub ddrc_ctrl: DdrcCtrl,
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pub two_rank_cfg: RW<u32>,
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pub hpr_reg: RW<u32>,
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pub lpr_reg: RW<u32>,
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@ -135,3 +141,16 @@ pub struct RegisterBlock {
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pub lpddr_ctrl3: RW<u32>,
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}
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impl RegisterBlock {
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pub unsafe fn new() -> &'static mut Self {
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&mut *(0xF8006000 as *mut _)
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}
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}
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register!(ddrc_ctrl, DdrcCtrl, RW, u32);
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register_bit!(ddrc_ctrl,
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/// `false` resets controller, `true` continues
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soft_rstb, 0);
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register_bit!(ddrc_ctrl, powerdown_en, 1);
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register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
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// (ddrc_ctrl) ...
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