forked from M-Labs/zynq-rs
add register_at! macro
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7e12468bf2
commit
351d18c10f
12
src/regs.rs
12
src/regs.rs
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@ -163,3 +163,15 @@ macro_rules! register_bits {
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}
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);
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}
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#[macro_export]
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macro_rules! register_at {
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($name: ident, $addr: expr, $ctor: ident) => (
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impl $name {
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pub fn $ctor() -> &'static mut Self {
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let addr = $addr as *mut Self;
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unsafe { &mut *addr }
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}
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}
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)
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}
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16
src/slcr.rs
16
src/slcr.rs
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@ -1,6 +1,6 @@
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#[allow(unused)]
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use crate::{register, register_bit, register_bits, regs::RegisterRW};
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use crate::{register, register_bit, register_bits, register_at, regs::RegisterW, regs::RegisterRW};
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pub enum PllSource {
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IoPll = 0b00,
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@ -13,13 +13,8 @@ register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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register_bits!(uart_clk_ctrl, srcsel, u8, 4, 5);
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register_at!(UartClkCtrl, 0xF8000154, new);
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impl UartClkCtrl {
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const ADDR: *mut Self = 0xF8000154 as *mut _;
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pub fn new() -> &'static mut Self {
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unsafe { &mut *Self::ADDR }
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}
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pub fn enable_uart0(&self) {
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self.modify(|_, w| {
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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@ -37,13 +32,8 @@ register_bit!(uart_rst_ctrl, uart0_ref_rst, 3);
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register_bit!(uart_rst_ctrl, uart1_ref_rst, 2);
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register_bit!(uart_rst_ctrl, uart0_cpu1x_rst, 1);
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register_bit!(uart_rst_ctrl, uart1_cpu1x_rst, 0);
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register_at!(UartRstCtrl, 0xF8000228, new);
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impl UartRstCtrl {
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const ADDR: *mut Self = 0xF8000228 as *mut _;
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pub fn new() -> &'static mut Self {
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unsafe { &mut *Self::ADDR }
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}
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pub fn reset_uart0(&self) {
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self.modify(|_, w| w.uart0_ref_rst(true));
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self.modify(|_, w| w.uart0_ref_rst(false));
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, regs::*};
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use crate::{register, register_bit, register_bits, register_at, regs::*};
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#[repr(C)]
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pub struct RegisterBlock {
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@ -23,6 +23,8 @@ pub struct RegisterBlock {
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pub unused1: RO<u32>,
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pub tx_fifo_trigger_level: RW<u32>,
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}
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register_at!(RegisterBlock, 0xE0000000, uart0);
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register_at!(RegisterBlock, 0xE0001000, uart1);
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register!(control, Control, RW, u32);
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register_bit!(control, rxrst, 0);
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@ -46,16 +48,3 @@ register_bits!(tx_rx_fifo, data, u32, 0, 31);
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register!(baud_rate_div, BaudRateDiv, RW, u32);
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register_bits!(baud_rate_div, bdiv, u8, 0, 7);
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impl RegisterBlock {
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const UART0: *mut Self = 0xE0000000 as *mut _;
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const UART1: *mut Self = 0xE0001000 as *mut _;
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pub fn uart0() -> &'static mut Self {
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unsafe { &mut *Self::UART0 }
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}
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pub fn uart1() -> &'static mut Self {
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unsafe { &mut *Self::UART1 }
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}
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}
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