forked from M-Labs/zynq-rs
zynq::flash: enable/disable spi for every transfer
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parent
e37659e4b3
commit
1e465250f5
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@ -12,6 +12,11 @@ pub use bytes::{BytesTransferExt, BytesTransfer};
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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const SINGLE_CAPACITY: u32 = 16 * 1024 * 1024;
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///Instruction: Read Configure Register
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const INST_RDCR: u8 = 0x3f;
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/// Instruction Read Identification
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const INST_RDID: u8 = 0x9F;
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pub struct LinearAddressing;
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pub struct Manual;
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@ -275,15 +280,12 @@ impl Flash<()> {
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.mode_en(true)
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// 2 devices
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.two_mem(true)
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// .sep_bus(true)
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.u_page(chip_index != 0)
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// Manual I/O mode
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.lq_mode(false)
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);
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self.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(true)
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);
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self.transition()
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}
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}
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@ -312,14 +314,16 @@ impl Flash<Manual> {
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self.transition()
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}
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/// Read Configuration Register
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pub fn rdcr(&mut self) -> u8 {
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self.transfer(0x35, core::iter::empty())
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self.transfer(INST_RDCR, core::iter::empty())
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.bytes_transfer().skip(1)
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.next().unwrap() as u8
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}
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/// Read Identifiaction
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pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::iter::Empty<u32>>>> {
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self.transfer(0x9f, core::iter::empty())
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self.transfer(INST_RDID, core::iter::empty())
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.bytes_transfer().skip(1)
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}
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@ -334,8 +338,8 @@ impl Flash<Manual> {
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// TODO:
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let args = Some(0u32);
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// Quad Read
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self.transfer(0xEB, args.into_iter())
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// Read
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self.transfer(0x03, args.into_iter())
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.bytes_transfer().skip(1).take(len)
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}
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}
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@ -350,6 +354,11 @@ impl<'a, Args: Iterator<Item = u32>> Transfer<'a, Args> {
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where
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Args: Iterator<Item = u32>,
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{
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flash.regs.config.modify(|_, w| w.pcs(false));
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flash.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(true)
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);
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while flash.regs.intr_status.read().rx_fifo_not_empty() {
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flash.regs.rx_data.read();
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}
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@ -364,10 +373,7 @@ impl<'a, Args: Iterator<Item = u32>> Transfer<'a, Args> {
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}
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}
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flash.regs.config.modify(|_, w| w
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.pcs(false)
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.man_start_com(true)
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);
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flash.regs.config.modify(|_, w| w.man_start_com(true));
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Transfer {
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flash,
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args,
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@ -377,9 +383,19 @@ impl<'a, Args: Iterator<Item = u32>> Transfer<'a, Args> {
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impl<'a, Args: Iterator<Item = u32>> Drop for Transfer<'a, Args> {
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fn drop(&mut self) {
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// Discard remaining rx_data
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while self.flash.regs.intr_status.read().rx_fifo_not_empty() {
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self.flash.regs.rx_data.read();
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}
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// Stop
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self.flash.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(false)
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);
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self.flash.regs.config.modify(|_, w| w
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.pcs(false)
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.man_start_com(true)
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.pcs(true)
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.man_start_com(false)
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);
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}
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}
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