forked from M-Labs/zynq-rs
libboard_zynq: remove unneeded Uart flush
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@ -192,15 +192,14 @@ impl Uart {
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self.regs.channel_sts.read().txfull()
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}
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pub fn tx_fifo_empty(&self) -> bool {
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self.regs.channel_sts.read().txempty()
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pub fn tx_idle(&self) -> bool {
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let status = self.regs.channel_sts.read();
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status.txempty() && !status.tactive()
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}
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}
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impl fmt::Write for Uart {
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fn write_str(&mut self, s: &str) -> Result<(), fmt::Error> {
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while !self.tx_fifo_empty() {}
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for b in s.bytes() {
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self.write_byte(b);
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}
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