Generate rust code
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33
README
33
README
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@ -1,5 +1,34 @@
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A simple script for parsing TRM register definition...
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Experimenting
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Pipe the `pdftotext -layout` output to the python script stdin, and specify the
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starting and ending address (absolute) of the registers.
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pdftotext -f 1436 -l 1438 -layout ug585-Zynq-7000-TRM.pdf - | python main.py
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This script can handle fields generation and description. This script is very
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hacky, have a lot of assumptions on the format of the PDF, so use with care,
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better check the output before you trust it.
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Example:
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pdftotext -f 1435 -l 1437 -layout ug585-Zynq-7000-TRM.pdf - | python main.py 0xF8F00000 0xF8F01FFF
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#[repr(C)]
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pub struct RegisterBlock {
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/// SCU Control Register
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pub scu_control_register: ScuControlRegister,
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/// SCU Configuration Register
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pub scu_configuration_register: ScuConfigurationRegister,
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}
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register!(scu_control_register, ScuControlRegister, RW, u32);
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register_bit!(scu_control_register, ic_standby_enable, 6);
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register_bit!(scu_control_register, scu_standby_enable, 5);
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register_bit!(scu_control_register, force_all_device_to_po, 4);
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register_bit!(scu_control_register, scu_speculative_linefil, 3);
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register_bit!(scu_control_register, scu_rams_parity_enab, 2);
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register_bit!(scu_control_register, address_filtering_enabl, 1);
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register_bit!(scu_control_register, scu_enable, 0);
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register!(scu_configuration_register, ScuConfigurationRegister, RO, u32);
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register_bits!(scu_configuration_register, tag_ram_sizes,u8, 8, 15);
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register_bits!(scu_configuration_register, cpus_smp,u8, 4, 7);
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register_bits!(scu_configuration_register, cpu_number,u8, 0, 1);
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147
main.py
147
main.py
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@ -167,18 +167,39 @@ def interpret(reg):
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assert len(expected) == 0
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return result
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def snake_to_camel(name: str):
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def to_camel(name: str):
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result = []
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start = True
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for c in name:
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if c == '_':
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start = True
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elif start:
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start = False
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result.append(c.upper())
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parts = name.split('_')
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for p in parts:
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if len(p) == 0:
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continue
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p = p[0].upper() + p[1:]
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result.append(p)
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return ''.join(result)
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def to_snake(text: str):
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if len(text) == 0:
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return ''
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if '_' in text:
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return text.lower()
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prev_upper = text[-1].isupper()
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result = []
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for c in reversed(text):
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current_upper = c.isupper()
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if prev_upper and not current_upper:
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if len(result) > 0 and result[-1] != '_':
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result.append('_')
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result.append(c.lower())
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elif not prev_upper and current_upper:
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result.append(c.lower())
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result.append('_')
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else:
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result.append(c.lower())
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return ''.join(result)
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prev_upper = current_upper
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if result[-1] == '_':
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result.pop()
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return ''.join(reversed(result))
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def access_to_type(access: str):
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access = access.upper()
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@ -192,14 +213,15 @@ def fields_to_rust(reg):
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fields = reg['fields']
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name_pattern = re.compile(r'(.+\w)\d+')
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access = access_to_type(reg['access'])
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assert reg['width'] in [8, 16, 32]
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if fields == []:
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return (f'{access}<u{reg["width"]}>', [])
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if len(fields) == 1:
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bits = fields[0]['bits']
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if bits[1] - bits[0] + 1 == reg['width']:
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return (f'{access_to_type(reg["access"])}<u{reg["width"]}>', [])
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namespace = reg['name'].lower()
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name = snake_to_camel(reg['name'])
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namespace = to_snake(reg['name'])
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name = to_camel(reg['name'])
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if 'similar' in reg:
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# remove the trailing digits
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name = name_pattern.fullmatch(name).group(1)
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@ -208,13 +230,16 @@ def fields_to_rust(reg):
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has_wtc = False
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lines = []
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for f in fields:
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field_name = f['name'].lower()
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field_name = to_snake(f['name'])
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if field_name in ['na', 'reserved']:
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continue
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field_access = f['access'].upper()
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[low, high] = f['bits']
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assert low <= high
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if field_access == 'WTC':
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has_wtc = True
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else:
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assert field_access in ['RO', 'RW', 'WO']
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for i in range(high - low + 1):
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bitmask |= 1 << (i + low)
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if low == high:
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@ -232,7 +257,7 @@ def fields_to_rust(reg):
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# we did not implement WTC for multiple bits, but could be done
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raise ValueError()
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lines.append(f'register_bits!({namespace}, {field_name},'
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f'{value_range}, {low}, {high});')
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f' {value_range}, {low}, {high});')
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if has_wtc:
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lines.insert(0, f'register!({namespace}, {name}, {access},'
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f' u{reg["width"]}, {bitmask});')
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@ -245,49 +270,71 @@ def emit_rust(base_addr, ending_addr, registers):
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current_addr = base_addr
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reserved_id = 0
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code = []
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fields = []
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def advance_to(addr, width):
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nonlocal current_addr, reserved_id, code
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padding = addr - current_addr
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assert padding >= 0
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if padding > 0:
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if padding % 4 == 0:
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code.append(f' unused{reserved_id}: [u32; {padding // 4}],')
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else:
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code.append(f' unused{reserved_id}: [u8; {padding}],')
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reserved_id += 1
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assert width in [8, 16, 32]
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current_addr += padding + width // 8
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for reg in registers:
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addr = int(reg['address'], 16)
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reg = interpret(reg)
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(typename, lines) = fields_to_rust(reg)
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description = reg['description']
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addr = reg['abs']
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if addr > ending_addr:
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break
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if 'similar' in reg:
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for r in reg['similar']:
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addr = r['abs']
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if addr > ending_addr:
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break
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if addr < base_addr:
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continue
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padding = addr - current_addr
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if padding > 0:
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if padding % 4 == 0:
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code.append(f'unused{reserved_id}: [RO<u32>; {padding // 4}],')
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advance_to(addr, reg['width'])
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# add description for the first one
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if description is not None:
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code.append(f' /// {description}')
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description = None
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if len(lines) > 0:
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fields.append('')
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fields += lines
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lines = []
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code.append(f' pub {reg["name"].lower()}: {typename},')
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else:
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code.append(f'unused{reserved_id}: [RO<u8>; {padding}],')
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reserved_id += 1
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access = ''
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unknown = False
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if reg['type'] == 'ro':
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access = 'RO'
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elif reg['type'] == 'wo':
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access = 'WO'
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elif reg['type'] in ['rw', 'mixed']:
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access = 'RW'
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else:
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access = reg['type']
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unknown = True
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size = int(reg['size'])
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if size not in [8, 16, 32]:
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unknown = True
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current_addr += padding + size // 8
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line = f"pub {reg['id'].lower()}: {access}<u{size}>,"
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if unknown:
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line = '// FIXME: ' + line
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code.append(f"/// {reg['description']}")
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code.append(line)
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addr = reg['abs']
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if addr > ending_addr:
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break
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if addr < base_addr:
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continue
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advance_to(addr, reg['width'])
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code.append(f' /// {description}')
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code.append(f' pub {reg["name"].lower()}: {typename},')
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if len(lines) > 0:
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fields.append('')
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fields += lines
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code.insert(0, '#[repr(C)]')
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code.insert(1, 'pub struct RegisterBlock {')
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code.append('}')
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code += fields
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return code
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parser = parse_registers()
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for line in sys.stdin:
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if __name__ == '__main__':
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if len(sys.argv) != 3:
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print("Please read the README")
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exit(0)
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parser = parse_registers()
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for line in sys.stdin:
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parser.send(line)
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v = end_iterator(parser)
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for reg in v:
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reg = interpret(reg)
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(name, lines) = fields_to_rust(reg)
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print(reg)
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print(name)
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print(lines)
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print('----')
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v = end_iterator(parser)
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for line in emit_rust(int(sys.argv[1], 0), int(sys.argv[2], 0), v):
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print(line)
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