forked from M-Labs/artiq-zynq
Compare commits
20 Commits
e65d4e0e84
...
cd12ebf9e9
|
|
@ -15,7 +15,7 @@ let
|
|||
version = "0.1.0";
|
||||
|
||||
src = ./src;
|
||||
cargoSha256 = "0p7n0kng0l3cgvfb6lss2pnljawh2gy7j1kvd9k072zyaqqjm58l";
|
||||
cargoSha256 = "1ybqf370xqcvs94zs542ydm5jszwrfqwlnr3xwn5yn2zp4cnv0vd";
|
||||
|
||||
nativeBuildInputs = [
|
||||
pkgs.gnumake
|
||||
|
|
|
|||
21
local_run.sh
21
local_run.sh
|
|
@ -3,19 +3,30 @@
|
|||
set -e
|
||||
|
||||
impure=0
|
||||
load_bitstream=1
|
||||
|
||||
while getopts "h:i" opt; do
|
||||
while getopts "h:i:l" opt; do
|
||||
case "$opt" in
|
||||
\?) exit 0
|
||||
\?) exit 1
|
||||
;;
|
||||
i) impure=1
|
||||
;;
|
||||
l) load_bitstream=0
|
||||
;;
|
||||
esac
|
||||
done
|
||||
|
||||
load_bitstream_cmd=""
|
||||
|
||||
cd openocd
|
||||
if [ $impure -eq 1 ]; then
|
||||
openocd -f zc706.cfg -c 'pld load 0 ../build/gateware/top.bit; load_image ../build/firmware/armv7-none-eabihf/release/szl; resume 0; exit'
|
||||
else
|
||||
openocd -f zc706.cfg -c 'pld load 0 ../result/top.bit; load_image ../result/szl.elf; resume 0; exit'
|
||||
if [ $load_bitstream -eq 1 ]; then
|
||||
load_bitstream_cmd="pld load 0 ../build/gateware/top.bit;"
|
||||
fi
|
||||
openocd -f zc706.cfg -c "$load_bitstream_cmd load_image ../build/firmware/armv7-none-eabihf/release/szl; resume 0; exit"
|
||||
else
|
||||
if [ $load_bitstream -eq 1 ]; then
|
||||
load_bitstream_cmd="pld load 0 ../result/top.bit;"
|
||||
fi
|
||||
openocd -f zc706.cfg -c "$load_bitstream_cmd load_image ../result/szl.elf; resume 0; exit"
|
||||
fi
|
||||
|
|
|
|||
|
|
@ -1,771 +0,0 @@
|
|||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00001402
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001081
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004159B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00033C03
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00034003
|
||||
mask_write 0XF8006134 0x000FFFFF 0x0002F400
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00030400
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000083
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000083
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x00000124
|
||||
mask_write 0XF800616C 0x001FFFFF 0x00000125
|
||||
mask_write 0XF8006170 0x001FFFFF 0x00000112
|
||||
mask_write 0XF8006174 0x001FFFFF 0x00000116
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000209
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000702
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000702
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000700
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000600
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00000302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00000303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00000303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00000201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00001402
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004159B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00033C03
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00034003
|
||||
mask_write 0XF8006134 0x000FFFFF 0x0002F400
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00030400
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000083
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000083
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x00000124
|
||||
mask_write 0XF800616C 0x001FFFFF 0x00000125
|
||||
mask_write 0XF8006170 0x001FFFFF 0x00000112
|
||||
mask_write 0XF8006174 0x001FFFFF 0x00000116
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000209
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000702
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000702
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000700
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000600
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00000302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00000303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00000303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00000201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00001402
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200400
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004159B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00033C03
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00034003
|
||||
mask_write 0XF8006134 0x000FFFFF 0x0002F400
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00030400
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000083
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000083
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x00000124
|
||||
mask_write 0XF800616C 0x001FFFFF 0x00000125
|
||||
mask_write 0XF8006170 0x001FFFFF 0x00000112
|
||||
mask_write 0XF8006174 0x001FFFFF 0x00000116
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C3
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000209
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000702
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000702
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000702
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000700
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000600
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000740 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00000302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00000302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00000303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00000303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00000303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000380
|
||||
mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||
mask_write 0XF80007BC 0x00003F01 0x00000201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666667
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
|
||||
ps7_post_config_1_0
|
||||
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
ps7_debug_1_0
|
||||
|
||||
}
|
||||
proc ps7_init {} {
|
||||
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
#
|
||||
# TCL to allow the Xilinx PS7 Init TCL code to run in OpenOCD.
|
||||
#
|
||||
|
||||
proc mrd { args } {
|
||||
if {[llength $args] == 0} {
|
||||
echo "mrd address \[count \[w|h|b\]\]"
|
||||
echo " Read <count> memory locations starting at <address>. Defaults to one word."
|
||||
return
|
||||
}
|
||||
set addr [lindex $args 0]
|
||||
set count 1
|
||||
set bits 32
|
||||
if {[llength $args] > 1} {
|
||||
set count [lindex $args 1]
|
||||
if {[llength $args] > 2} {
|
||||
switch [lindex $args 2] {
|
||||
w { set bits 32 }
|
||||
h { set bits 16 }
|
||||
b { set bits 8 }
|
||||
default { set bits 32 }
|
||||
}
|
||||
}
|
||||
}
|
||||
mem2array x $bits $addr $count
|
||||
set nibbles [expr {$bits / 4}]
|
||||
set bytes [expr {$bits / 8}]
|
||||
set result {}
|
||||
foreach {idx elmt} $x {
|
||||
append result [format "%08x: %0*x\n" [expr {$addr + $idx * $bytes}] $nibbles $elmt]
|
||||
}
|
||||
return $result
|
||||
}
|
||||
|
||||
proc mwr { args } {
|
||||
set addr [lindex $args 1]
|
||||
set data [lindex $args 2]
|
||||
mww $addr $data
|
||||
}
|
||||
|
||||
proc mask_write { addr mask value } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & ~$mask}]
|
||||
#echo "curval = [format 0x%08x $curval] maskedval = [format 0x%08x $maskedval]"
|
||||
set writeval(0) [expr {$maskedval | $value}]
|
||||
#echo " $addr <= [format 0x%08x $writeval(0)] ([format 0x%08x $curval]: [format 0x%08x $mask]/[format 0x%08x $value])"
|
||||
array2mem writeval 32 $addr 1
|
||||
}
|
||||
|
||||
proc xilinx_ps7_init { } {
|
||||
poll off
|
||||
reset init
|
||||
reset halt
|
||||
targets zynq.cpu.0
|
||||
sleep 100
|
||||
halt
|
||||
ps7_debug
|
||||
ps7_init
|
||||
ps7_post_config
|
||||
poll on
|
||||
}
|
||||
|
|
@ -1,13 +1,10 @@
|
|||
source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
|
||||
source [find xilinx-tcl.cfg]
|
||||
adapter_khz 1000
|
||||
|
||||
set PL_TAPID 0x23731093
|
||||
set SMP 1
|
||||
|
||||
source ./zynq-7000.cfg
|
||||
source ./xilinx-tcl.cfg
|
||||
source ./ps7_init.tcl
|
||||
|
||||
reset_config srst_only srst_open_drain
|
||||
adapter_nsrst_assert_width 250
|
||||
|
|
@ -34,7 +31,7 @@ pld device virtex2 zynq.tap 1
|
|||
init
|
||||
xc7_program zynq.tap
|
||||
|
||||
xilinx_ps7_init
|
||||
reset halt
|
||||
|
||||
# Disable MMU
|
||||
targets $_TARGETNAME_1
|
||||
|
|
|
|||
|
|
@ -93,119 +93,3 @@ if { $_SMP } {
|
|||
-dbgbase 0x80092000
|
||||
target smp $_TARGETNAME_0 $_TARGETNAME_1
|
||||
}
|
||||
|
||||
#
|
||||
# Hack to get the registers into a stable state when first booting a zynq in
|
||||
# JTAG mode. If r11 is pointing to an invalid address and you use gdb to set a
|
||||
# register the write will fail because gdb attempts to scan or unwind the
|
||||
# current frame and the bad address seems to lock the bus up. This code puts
|
||||
# the registers into the OCM and hopefull safe.
|
||||
#
|
||||
proc zynq_clear_registers { target } {
|
||||
echo "Zynq-7000 Series setup: $target"
|
||||
set _OCM_END 0x0003FFF0
|
||||
mww phys 0xF8007000 0x4E00E07F
|
||||
reg r0 0
|
||||
reg r1 0
|
||||
reg r2 0
|
||||
reg r3 0
|
||||
reg r4 0
|
||||
reg r5 0
|
||||
reg r6 0
|
||||
reg r7 0
|
||||
reg r8 0
|
||||
reg r9 0
|
||||
reg r10 0
|
||||
reg r11 $_OCM_END
|
||||
reg sp_svc $_OCM_END
|
||||
reg lr_svc $_OCM_END
|
||||
reg sp_abt $_OCM_END
|
||||
reg lr_abt $_OCM_END
|
||||
reg sp_und $_OCM_END
|
||||
reg lr_und $_OCM_END
|
||||
}
|
||||
|
||||
proc zynq_disable_mmu_and_caches { target } {
|
||||
# arm mcr pX op1 CRn CRm op2 value
|
||||
echo "Disable MMU and caches"
|
||||
# Invalidate caches
|
||||
catch {
|
||||
$target arm mcr 15 0 7 5 0 0
|
||||
$target arm mcr 15 0 7 7 0 0
|
||||
# Invalidate all TLBs
|
||||
$target arm mcr 15 0 8 5 0 0
|
||||
$target arm mcr 15 0 8 6 0 0
|
||||
$target arm mcr 15 0 8 7 0 0
|
||||
$target arm mcr 15 4 8 3 0 0
|
||||
$target arm mcr 15 4 8 7 0 0
|
||||
set cp [$target arm mrc 15 0 1 0 0]
|
||||
echo "SCTRL => [format 0x%x $cp]"
|
||||
set mask [expr 1 << 29 | 1 << 12 | 1 << 11 | 1 << 2 | 1 << 1 | 1 << 0]
|
||||
set cp [expr ($cp & ~$mask)]
|
||||
$target arm mcr 15 0 1 0 0 $cp
|
||||
echo "SCTRL <= [format 0x%x $cp]"
|
||||
}
|
||||
}
|
||||
|
||||
proc zynq_boot_ocm_setup { } {
|
||||
#
|
||||
# Enable the OCM
|
||||
#
|
||||
echo "Zynq Boot OCM setup"
|
||||
catch {
|
||||
mww phys 0xF8000008 0xDF0D
|
||||
mww phys 0xF8000238 0
|
||||
mww phys 0xF8000910 0xC
|
||||
}
|
||||
}
|
||||
|
||||
proc zynq_rtems_setup { } {
|
||||
cache_config l2x 0xF8F02000 8
|
||||
cortex_a maskisr on
|
||||
}
|
||||
|
||||
proc zynq_restart { wait } {
|
||||
global _SMP
|
||||
global _TARGETNAME_0
|
||||
global _TARGETNAME_1
|
||||
set target0 $_TARGETNAME_0
|
||||
set target1 $_TARGETNAME_1
|
||||
echo "Zynq reset, resetting the board ... "
|
||||
poll off
|
||||
#
|
||||
# Issue the reset via the SLCR
|
||||
#
|
||||
catch {
|
||||
mww phys 0xF8000008 0xDF0D
|
||||
mww phys 0xF8000200 1
|
||||
}
|
||||
echo "Zynq reset waiting for $wait msecs ... "
|
||||
sleep $wait
|
||||
#
|
||||
# Reconnect the DAP etc due to the reset.
|
||||
#
|
||||
$target0 cortex_a dbginit
|
||||
$target0 arm core_state arm
|
||||
if { $_SMP } {
|
||||
$target1 arm core_state arm
|
||||
$target1 cortex_a dbginit
|
||||
cortex_a smp_off
|
||||
}
|
||||
poll on
|
||||
#
|
||||
# We can now halt the core.
|
||||
#
|
||||
if { $_SMP } {
|
||||
targets $target1
|
||||
halt
|
||||
}
|
||||
targets $target0
|
||||
halt
|
||||
zynq_rtems_setup
|
||||
}
|
||||
|
||||
proc zynq_gdb_attach { target } {
|
||||
catch {
|
||||
halt
|
||||
}
|
||||
}
|
||||
|
|
@ -4,27 +4,49 @@ set -e
|
|||
|
||||
target_host="rpi-4.m-labs.hk"
|
||||
impure=0
|
||||
pure_dir="result"
|
||||
impure_dir="build"
|
||||
sshopts=""
|
||||
load_bitstream=1
|
||||
|
||||
while getopts "h:i" opt; do
|
||||
while getopts "h:id:o:l" opt; do
|
||||
case "$opt" in
|
||||
\?) exit 0
|
||||
\?) exit 1
|
||||
;;
|
||||
h) target_host=$OPTARG
|
||||
;;
|
||||
i) impure=1
|
||||
;;
|
||||
d) pure_dir=$OPTARG;
|
||||
impure_dir=$OPTARG;
|
||||
;;
|
||||
o) sshopts=$OPTARG
|
||||
;;
|
||||
l) load_bitstream=0
|
||||
;;
|
||||
esac
|
||||
done
|
||||
|
||||
target_folder=/tmp/zynq-\$USER
|
||||
|
||||
ssh $target_host "mkdir -p $target_folder"
|
||||
rsync openocd/* $target_host:$target_folder
|
||||
if [ $impure -eq 1 ]; then
|
||||
rsync build/firmware/armv7-none-eabihf/release/szl $target_host:$target_folder/szl.elf
|
||||
rsync build/gateware/top.bit $target_host:$target_folder
|
||||
else
|
||||
rsync -L result/szl.elf $target_host:$target_folder
|
||||
rsync -L result/top.bit $target_host:$target_folder
|
||||
target_folder="/tmp/zynq-$USER"
|
||||
load_bitstream_cmd=""
|
||||
if [ $load_bitstream -eq 1 ]; then
|
||||
load_bitstream_cmd="pld load 0 top.bit;"
|
||||
fi
|
||||
ssh $target_host "cd $target_folder; openocd -f zc706.cfg -c 'pld load 0 top.bit; load_image szl.elf; resume 0; exit'"
|
||||
|
||||
echo "Creating $target_folder..."
|
||||
ssh $sshopts $target_host "mkdir -p $target_folder"
|
||||
echo "Copying files..."
|
||||
rsync -e "ssh $sshopts" openocd/* $target_host:$target_folder
|
||||
if [ $impure -eq 1 ]; then
|
||||
rsync -e "ssh $sshopts" $impure_dir/firmware/armv7-none-eabihf/release/szl $target_host:$target_folder/szl.elf
|
||||
if [ $load_bitstream -eq 1 ]; then
|
||||
rsync -e "ssh $sshopts" $impure_dir/gateware/top.bit $target_host:$target_folder
|
||||
fi
|
||||
else
|
||||
rsync -e "ssh $sshopts" -Lc $pure_dir/szl.elf $target_host:$target_folder
|
||||
if [ $load_bitstream -eq 1 ]; then
|
||||
rsync -e "ssh $sshopts" -Lc $pure_dir/top.bit $target_host:$target_folder
|
||||
fi
|
||||
fi
|
||||
echo "Programming board..."
|
||||
ssh $sshopts $target_host "cd $target_folder; openocd -f zc706.cfg -c'$load_bitstream_cmd load_image szl.elf; resume 0; exit'"
|
||||
|
|
|
|||
|
|
@ -37,9 +37,9 @@ checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de"
|
|||
|
||||
[[package]]
|
||||
name = "cc"
|
||||
version = "1.0.54"
|
||||
version = "1.0.57"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "7bbb73db36c1246e9034e307d0fba23f9a2e251faa47ade70c1bd252220c8311"
|
||||
checksum = "0fde55d2a2bfaa4c9668bbc63f531fbdeee3ffe188f4662511ce2c22b3eedebe"
|
||||
|
||||
[[package]]
|
||||
name = "cfg-if"
|
||||
|
|
@ -200,7 +200,7 @@ dependencies = [
|
|||
[[package]]
|
||||
name = "libasync"
|
||||
version = "0.0.0"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#9fcf9243f2dd2e9fcd61d17ddb1d6d495a68893f"
|
||||
dependencies = [
|
||||
"embedded-hal",
|
||||
"libcortex_a9",
|
||||
|
|
@ -212,7 +212,7 @@ dependencies = [
|
|||
[[package]]
|
||||
name = "libboard_zynq"
|
||||
version = "0.0.0"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#9fcf9243f2dd2e9fcd61d17ddb1d6d495a68893f"
|
||||
dependencies = [
|
||||
"bit_field",
|
||||
"embedded-hal",
|
||||
|
|
@ -236,7 +236,7 @@ dependencies = [
|
|||
[[package]]
|
||||
name = "libcortex_a9"
|
||||
version = "0.0.0"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#9fcf9243f2dd2e9fcd61d17ddb1d6d495a68893f"
|
||||
dependencies = [
|
||||
"bit_field",
|
||||
"libregister",
|
||||
|
|
@ -245,7 +245,7 @@ dependencies = [
|
|||
[[package]]
|
||||
name = "libregister"
|
||||
version = "0.0.0"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#9fcf9243f2dd2e9fcd61d17ddb1d6d495a68893f"
|
||||
dependencies = [
|
||||
"bit_field",
|
||||
"vcell",
|
||||
|
|
@ -255,7 +255,7 @@ dependencies = [
|
|||
[[package]]
|
||||
name = "libsupport_zynq"
|
||||
version = "0.0.0"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#9fcf9243f2dd2e9fcd61d17ddb1d6d495a68893f"
|
||||
dependencies = [
|
||||
"compiler_builtins",
|
||||
"libboard_zynq",
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ use core::str::Utf8Error;
|
|||
use alloc::rc::Rc;
|
||||
use alloc::sync::Arc;
|
||||
use alloc::{vec, vec::Vec, string::String};
|
||||
use log::{debug, warn, error};
|
||||
use log::{info, warn, error};
|
||||
|
||||
use num_derive::{FromPrimitive, ToPrimitive};
|
||||
use num_traits::{FromPrimitive, ToPrimitive};
|
||||
|
|
@ -78,12 +78,6 @@ enum Reply {
|
|||
ClockFailure = 15,
|
||||
}
|
||||
|
||||
async fn write_chunk(stream: &TcpStream, chunk: &[u8]) -> Result<()> {
|
||||
write_i32(stream, chunk.len() as i32).await?;
|
||||
stream.send(chunk.iter().copied()).await?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
async fn write_header(stream: &TcpStream, reply: Reply) -> Result<()> {
|
||||
stream.send([0x5a, 0x5a, 0x5a, 0x5a, reply.to_u8().unwrap()].iter().copied()).await?;
|
||||
Ok(())
|
||||
|
|
@ -96,7 +90,7 @@ async fn read_request(stream: &TcpStream, allow_close: bool) -> Result<Option<Re
|
|||
return Err(Error::UnexpectedPattern),
|
||||
Err(smoltcp::Error::Illegal) => {
|
||||
if allow_close {
|
||||
debug!("peer closed connection");
|
||||
info!("peer closed connection");
|
||||
return Ok(None);
|
||||
} else {
|
||||
error!("peer unexpectedly closed connection");
|
||||
|
|
@ -216,7 +210,7 @@ async fn handle_run_kernel(stream: &TcpStream, control: &Rc<RefCell<kernel::Cont
|
|||
|
||||
async fn handle_connection(stream: &TcpStream, control: Rc<RefCell<kernel::Control>>) -> Result<()> {
|
||||
expect(stream, b"ARTIQ coredev\n").await?;
|
||||
debug!("received connection");
|
||||
info!("received connection");
|
||||
loop {
|
||||
let request = read_request(stream, true).await?;
|
||||
if request.is_none() {
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
use core::{ptr, mem};
|
||||
use log::{debug, error};
|
||||
use log::{debug, info, error};
|
||||
use alloc::{vec::Vec, sync::Arc};
|
||||
use cslice::CSlice;
|
||||
|
||||
use libcortex_a9::{cache::dcci_slice, mutex::Mutex, sync_channel::{self, sync_channel}};
|
||||
use libcortex_a9::{enable_fpu, cache::dcci_slice, mutex::Mutex, sync_channel::{self, sync_channel}};
|
||||
use libsupport_zynq::boot::Core1;
|
||||
|
||||
use dyld;
|
||||
|
|
@ -288,17 +288,7 @@ fn resolve(required: &[u8]) -> Option<u32> {
|
|||
pub fn main_core1() {
|
||||
debug!("Core1 started");
|
||||
|
||||
unsafe {
|
||||
llvm_asm!("
|
||||
mrc p15, 0, r1, c1, c0, 2
|
||||
orr r1, r1, (0b1111<<20)
|
||||
mcr p15, 0, r1, c1, c0, 2
|
||||
|
||||
vmrs r1, fpexc
|
||||
orr r1, r1, (1<<30)
|
||||
vmsr fpexc, r1
|
||||
":::"r1");
|
||||
}
|
||||
enable_fpu();
|
||||
debug!("FPU enabled on Core1");
|
||||
|
||||
let mut core1_tx = None;
|
||||
|
|
@ -349,7 +339,7 @@ pub fn main_core1() {
|
|||
}
|
||||
},
|
||||
Message::StartRequest => {
|
||||
debug!("kernel starting");
|
||||
info!("kernel starting");
|
||||
if let Some(__modinit__) = current_modinit {
|
||||
unsafe {
|
||||
KERNEL_CHANNEL_0TO1 = mem::transmute(&mut core1_rx);
|
||||
|
|
@ -362,7 +352,7 @@ pub fn main_core1() {
|
|||
KERNEL_CHANNEL_1TO0 = ptr::null_mut();
|
||||
}
|
||||
}
|
||||
debug!("kernel finished");
|
||||
info!("kernel finished");
|
||||
core1_tx.send(Message::KernelFinished);
|
||||
}
|
||||
_ => error!("Core1 received unexpected message: {:?}", message),
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![recursion_limit="1024"] // for futures_util::select!
|
||||
#![feature(llvm_asm)]
|
||||
#![feature(alloc_error_handler)]
|
||||
#![feature(panic_info_message)]
|
||||
|
||||
|
|
@ -10,7 +9,7 @@ extern crate alloc;
|
|||
use core::{cmp, str};
|
||||
use log::{info, error};
|
||||
|
||||
use libboard_zynq::{timer::GlobalTimer, logger, devc};
|
||||
use libboard_zynq::{timer::GlobalTimer, logger, devc, slcr};
|
||||
use libsupport_zynq::ram;
|
||||
|
||||
mod sd_reader;
|
||||
|
|
@ -73,6 +72,10 @@ pub fn main_core0() {
|
|||
// Do not load again: assume that the gateware already present is
|
||||
// what we want (e.g. gateware configured via JTAG before PS
|
||||
// startup, or by FSBL).
|
||||
// Make sure that the PL/PS interface is enabled (e.g. OpenOCD does not enable it).
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
slcr.init_postload_fpga();
|
||||
});
|
||||
} else {
|
||||
// Load from SD card
|
||||
match load_pl::load_bitstream_from_sd() {
|
||||
|
|
|
|||
|
|
@ -123,4 +123,3 @@ pub async fn write_chunk(stream: &TcpStream, value: &[u8]) -> Result<()> {
|
|||
stream.send(value.iter().copied()).await?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
use core::str;
|
||||
use core::future::Future;
|
||||
use cslice::{CSlice, CMutSlice};
|
||||
use log::debug;
|
||||
use log::trace;
|
||||
|
||||
use core_io::{Write, Error};
|
||||
use libboard_zynq::smoltcp;
|
||||
|
|
@ -93,7 +93,7 @@ pub async fn recv_return<F>(stream: &TcpStream, tag_bytes: &[u8], data: *mut (),
|
|||
where F: Future<Output=*mut ()>
|
||||
{
|
||||
let mut it = TagIterator::new(tag_bytes);
|
||||
debug!("recv ...->{}", it);
|
||||
trace!("recv ...->{}", it);
|
||||
|
||||
let tag = it.next().expect("truncated tag");
|
||||
let mut data = data;
|
||||
|
|
@ -187,7 +187,7 @@ pub fn send_args<W>(writer: &mut W, service: u32, tag_bytes: &[u8], data: *const
|
|||
|
||||
let mut args_it = TagIterator::new(arg_tags_bytes);
|
||||
let return_it = TagIterator::new(return_tag_bytes);
|
||||
debug!("send<{}>({})->{}", service, args_it, return_it);
|
||||
trace!("send<{}>({})->{}", service, args_it, return_it);
|
||||
|
||||
writer.write_u32(service)?;
|
||||
for index in 0.. {
|
||||
|
|
|
|||
|
|
@ -1,14 +1,13 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(llvm_asm)]
|
||||
|
||||
extern crate log;
|
||||
|
||||
use core::mem;
|
||||
use log::{info, error};
|
||||
use log::{debug, info, error};
|
||||
use cstr_core::CStr;
|
||||
|
||||
use libcortex_a9::cache::dcci_slice;
|
||||
use libcortex_a9::{enable_fpu, cache::dcci_slice};
|
||||
use libboard_zynq::{
|
||||
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
|
||||
logger,
|
||||
|
|
@ -37,18 +36,9 @@ pub fn main_core0() {
|
|||
log::set_max_level(log::LevelFilter::Debug);
|
||||
info!("Simple Zynq Loader starting...");
|
||||
|
||||
unsafe {
|
||||
llvm_asm!("
|
||||
mrc p15, 0, r1, c1, c0, 2
|
||||
orr r1, r1, (0b1111<<20)
|
||||
mcr p15, 0, r1, c1, c0, 2
|
||||
enable_fpu();
|
||||
debug!("FPU enabled on Core0");
|
||||
|
||||
vmrs r1, fpexc
|
||||
orr r1, r1, (1<<30)
|
||||
vmsr fpexc, r1
|
||||
":::"r1");
|
||||
}
|
||||
info!("FPU enabled on Core0");
|
||||
const CPU_FREQ: u32 = 800_000_000;
|
||||
|
||||
ArmPll::setup(2 * CPU_FREQ);
|
||||
|
|
|
|||
Loading…
Reference in New Issue