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artiq-zynq
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use fpu_enable from zc706

core0-buffer
Sebastien Bourdeauducq 2020-07-06 00:18:28 +08:00
parent de8da59e56
commit 3bd4643009
5 changed files with 14 additions and 35 deletions
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2
default.nix
View File

@ -15,7 +15,7 @@ let
version = "0.1.0";
src = ./src;
cargoSha256 = "0p7n0kng0l3cgvfb6lss2pnljawh2gy7j1kvd9k072zyaqqjm58l";
cargoSha256 = "04f45x75vb2ccn8h5pclng913747jx3qqv5d7fip5dhqw90nb8gn";
nativeBuildInputs = [
pkgs.gnumake

14
src/Cargo.lock generated
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@ -37,9 +37,9 @@ checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de"
[[package]]
name = "cc"
version = "1.0.54"
version = "1.0.57"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "7bbb73db36c1246e9034e307d0fba23f9a2e251faa47ade70c1bd252220c8311"
checksum = "0fde55d2a2bfaa4c9668bbc63f531fbdeee3ffe188f4662511ce2c22b3eedebe"
[[package]]
name = "cfg-if"
@ -200,7 +200,7 @@ dependencies = [
[[package]]
name = "libasync"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#90e33f688ab8de54173caca1e8d9a7357def5df8"
dependencies = [
"embedded-hal",
"libcortex_a9",
@ -212,7 +212,7 @@ dependencies = [
[[package]]
name = "libboard_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#90e33f688ab8de54173caca1e8d9a7357def5df8"
dependencies = [
"bit_field",
"embedded-hal",
@ -236,7 +236,7 @@ dependencies = [
[[package]]
name = "libcortex_a9"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#90e33f688ab8de54173caca1e8d9a7357def5df8"
dependencies = [
"bit_field",
"libregister",
@ -245,7 +245,7 @@ dependencies = [
[[package]]
name = "libregister"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#90e33f688ab8de54173caca1e8d9a7357def5df8"
dependencies = [
"bit_field",
"vcell",
@ -255,7 +255,7 @@ dependencies = [
[[package]]
name = "libsupport_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
source = "git+https://git.m-labs.hk/M-Labs/zc706.git#90e33f688ab8de54173caca1e8d9a7357def5df8"
dependencies = [
"compiler_builtins",
"libboard_zynq",

14
src/runtime/src/kernel.rs
View File

@ -3,7 +3,7 @@ use log::{debug, info, error};
use alloc::{vec::Vec, sync::Arc};
use cslice::CSlice;
use libcortex_a9::{cache::dcci_slice, mutex::Mutex, sync_channel::{self, sync_channel}};
use libcortex_a9::{enable_fpu, cache::dcci_slice, mutex::Mutex, sync_channel::{self, sync_channel}};
use libsupport_zynq::boot::Core1;
use dyld;
@ -288,17 +288,7 @@ fn resolve(required: &[u8]) -> Option<u32> {
pub fn main_core1() {
debug!("Core1 started");
unsafe {
llvm_asm!("
mrc p15, 0, r1, c1, c0, 2
orr r1, r1, (0b1111<<20)
mcr p15, 0, r1, c1, c0, 2
vmrs r1, fpexc
orr r1, r1, (1<<30)
vmsr fpexc, r1
":::"r1");
}
enable_fpu();
debug!("FPU enabled on Core1");
let mut core1_tx = None;

1
src/runtime/src/main.rs
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@ -1,7 +1,6 @@
#![no_std]
#![no_main]
#![recursion_limit="1024"] // for futures_util::select!
#![feature(llvm_asm)]
#![feature(alloc_error_handler)]
#![feature(panic_info_message)]

18
src/szl/src/main.rs
View File

@ -1,14 +1,13 @@
#![no_std]
#![no_main]
#![feature(llvm_asm)]
extern crate log;
use core::mem;
use log::{info, error};
use log::{debug, info, error};
use cstr_core::CStr;
use libcortex_a9::cache::dcci_slice;
use libcortex_a9::{enable_fpu, cache::dcci_slice};
use libboard_zynq::{
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
logger,
@ -37,18 +36,9 @@ pub fn main_core0() {
log::set_max_level(log::LevelFilter::Debug);
info!("Simple Zynq Loader starting...");
unsafe {
llvm_asm!("
mrc p15, 0, r1, c1, c0, 2
orr r1, r1, (0b1111<<20)
mcr p15, 0, r1, c1, c0, 2
enable_fpu();
debug!("FPU enabled on Core0");
vmrs r1, fpexc
orr r1, r1, (1<<30)
vmsr fpexc, r1
":::"r1");
}
info!("FPU enabled on Core0");
const CPU_FREQ: u32 = 800_000_000;
ArmPll::setup(2 * CPU_FREQ);