forked from M-Labs/artiq-zynq
satman: implement boot file rewrite sequence
This commit is contained in:
parent
5cb565a7e0
commit
2985875f9a
2
src/Cargo.lock
generated
2
src/Cargo.lock
generated
@ -559,7 +559,9 @@ name = "satman"
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version = "0.0.0"
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version = "0.0.0"
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dependencies = [
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dependencies = [
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"build_zynq",
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"build_zynq",
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"byteorder",
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"core_io",
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"core_io",
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"crc",
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"cslice",
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"cslice",
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"embedded-hal",
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"embedded-hal",
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"io",
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"io",
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@ -15,7 +15,9 @@ build_zynq = { path = "../libbuild_zynq" }
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[dependencies]
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[dependencies]
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log = { version = "0.4", default-features = false }
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log = { version = "0.4", default-features = false }
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byteorder = { version = "1.3", default-features = false }
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core_io = { version = "0.1", features = ["collections"] }
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core_io = { version = "0.1", features = ["collections"] }
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crc = { version = "1.7", default-features = false }
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cslice = "0.3"
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cslice = "0.3"
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embedded-hal = "0.2"
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embedded-hal = "0.2"
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@ -4,7 +4,9 @@
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#[macro_use]
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#[macro_use]
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extern crate log;
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extern crate log;
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extern crate byteorder;
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extern crate core_io;
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extern crate core_io;
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extern crate crc;
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extern crate cslice;
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extern crate cslice;
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extern crate embedded_hal;
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extern crate embedded_hal;
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@ -1144,7 +1146,7 @@ fn process_aux_packet(
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},
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},
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)
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)
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} else {
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} else {
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
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}
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}
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}
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}
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}
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}
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@ -1280,6 +1282,53 @@ fn process_aux_packet(
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error!("debug allocator not supported on zynq device");
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error!("debug allocator not supported on zynq device");
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
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}
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}
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drtioaux::Packet::CoreMgmtFlashRequest {
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destination: _destination,
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last,
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length,
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data,
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} => {
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forward!(
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router,
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_routing_table,
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_destination,
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*rank,
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*self_destination,
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_repeaters,
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&packet,
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timer
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);
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core_manager.add_image_data(&data, length as usize);
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if last {
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtDropLink)
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} else {
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
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}
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}
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drtioaux::Packet::CoreMgmtDropLinkAck {
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destination: _destination,
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} => {
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forward!(
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router,
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_routing_table,
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_destination,
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*rank,
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*self_destination,
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_repeaters,
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&packet,
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timer
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);
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unsafe {
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csr::gt_drtio::txenable_write(0);
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}
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core_manager.write_image();
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info!("reboot imminent");
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slcr::reboot();
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Ok(())
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}
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p => {
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p => {
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warn!("received unexpected aux packet: {:?}", p);
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warn!("received unexpected aux packet: {:?}", p);
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@ -1,5 +1,7 @@
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use alloc::vec::Vec;
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use alloc::vec::Vec;
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use byteorder::{ByteOrder, NativeEndian};
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use crc::crc32;
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use io::{Cursor, ProtoRead, ProtoWrite};
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use io::{Cursor, ProtoRead, ProtoWrite};
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use libboard_artiq::{drtioaux_proto::SAT_PAYLOAD_MAX_SIZE,
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use libboard_artiq::{drtioaux_proto::SAT_PAYLOAD_MAX_SIZE,
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logger::{BufferLogger, LogBufferRef}};
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logger::{BufferLogger, LogBufferRef}};
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@ -48,6 +50,7 @@ pub struct Manager<'a> {
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last_log: Sliceable,
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last_log: Sliceable,
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config_payload: Cursor<Vec<u8>>,
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config_payload: Cursor<Vec<u8>>,
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last_value: Sliceable,
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last_value: Sliceable,
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image_payload: Vec<u8>,
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}
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}
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impl<'a> Manager<'_> {
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impl<'a> Manager<'_> {
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@ -57,6 +60,7 @@ impl<'a> Manager<'_> {
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last_log: Sliceable::new(0, Vec::new()),
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last_log: Sliceable::new(0, Vec::new()),
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config_payload: Cursor::new(Vec::new()),
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config_payload: Cursor::new(Vec::new()),
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last_value: Sliceable::new(0, Vec::new()),
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last_value: Sliceable::new(0, Vec::new()),
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image_payload: Vec::new(),
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}
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}
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}
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}
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@ -113,4 +117,31 @@ impl<'a> Manager<'_> {
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.map(|()| debug!("erase success"))
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.map(|()| debug!("erase success"))
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.map_err(|err| warn!("failed to erase: {:?}", err))
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.map_err(|err| warn!("failed to erase: {:?}", err))
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}
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}
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pub fn add_image_data(&mut self, data: &[u8], data_len: usize) {
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self.image_payload.extend(&data[..data_len]);
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}
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pub fn write_image(&self) {
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let mut image = self.image_payload.clone();
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let image_ref = &image[..];
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let bin_len = image.len() - 4;
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let (image_ref, expected_crc) = {
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let (image_ref, crc_slice) = image_ref.split_at(bin_len);
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(image_ref, NativeEndian::read_u32(crc_slice))
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};
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let actual_crc = crc32::checksum_ieee(image_ref);
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if actual_crc == expected_crc {
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image.truncate(bin_len);
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self.cfg.write("boot", image).expect("failed to write boot image");
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} else {
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panic!(
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"CRC failed in SDRAM (actual {:08x}, expected {:08x})",
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actual_crc, expected_crc
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);
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}
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}
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}
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}
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