artiq-zynq/src/runtime/link.x

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ENTRY(Reset);
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MEMORY
{
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SDRAM : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
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}
SECTIONS
{
__text_start = .;
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.text :
{
KEEP(*(.text.exceptions));
*(.text.boot);
*(.text .text.*);
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} > SDRAM
__text_end = .;
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > SDRAM
__exidx_end = .;
.ARM.extab :
{
* (.ARM.extab*)
} > SDRAM
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.rodata : ALIGN(4)
{
*(.rodata .rodata.*);
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} > SDRAM
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.data : ALIGN(4)
{
*(.data .data.*);
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} > SDRAM
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.bss (NOLOAD) : ALIGN(4)
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{
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__bss_start = .;
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*(.bss .bss.*);
. = ALIGN(4);
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__bss_end = .;
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} > SDRAM
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.heap (NOLOAD) : ALIGN(8)
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{
__heap0_start = .;
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. += 0x8000000;
__heap0_end = .;
__heap1_start = .;
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. += 0x8000000;
__heap1_end = .;
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} > SDRAM
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.stack1 (NOLOAD) : ALIGN(8)
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{
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__stack1_end = .;
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. += 0x1000000;
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__stack1_start = .;
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} > SDRAM
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.stack0 (NOLOAD) : ALIGN(8)
{
__stack0_end = .;
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. += 0x20000;
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__stack0_start = .;
} > SDRAM
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.irq_stack1 (NOLOAD) : ALIGN(8)
{
__irq_stack1_end = .;
. += 0x100;
__irq_stack1_start = .;
} > SDRAM
.irq_stack0 (NOLOAD) : ALIGN(8)
{
__irq_stack0_end = .;
. += 0x100;
__irq_stack0_start = .;
} > SDRAM
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}