forked from M-Labs/web2019
refactor(Migen): Reviews layout and md file
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@ -9,89 +9,74 @@ logo_size = 125
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title = "Migen"
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{% centerp(safe=true) %}
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<h5 class="mb-5">Migen is a Python-based tool that automates further the VLSI design process.</h5>
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{% layout_centered_content() %}
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##### Migen is a Python-based tool that automates further the VLSI design process.
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{% end %}
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{% layoutlr1() %}
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<div class="row d-flex align-items-center mt-5 mb-5">
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{% layout_div(css="col-12 col-md-6") %}
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<div class="col-12 col-md-6">
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<p>
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Despite being faster than schematics entry, hardware design with Verilog and VHDL remains tedious and inefficient for several reasons. The event-driven model introduces issues and manual coding that are unnecessary for synchronous circuits, which represent the lion's share of today's logic designs. Counter-intuitive arithmetic rules result in steeper learning curves and provide a fertile ground for subtle bugs in designs. Finally, support for procedural generation of logic (metaprogramming) through "generate" statements is very limited and restricts the ways code can be made generic, reused and organized.
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</p>
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</div>
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<div class="col-12 col-md-6">
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<p>
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{% end %}
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{% layout_div(css="col-12 col-md-6") %}
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To address those issues, we have developed the Migen FHDL library that replaces the event-driven paradigm with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and most importantly allows the design's logic to be constructed by a Python program. This last point enables hardware designers to take advantage of the richness of the Python language - object oriented programming, function parameters, generators, operator overloading, libraries, etc. - to build well organized, reusable and elegant designs.
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</p>
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{% end %}
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</div>
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{% layout_centered_content(min_width=true) %}
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Other Migen libraries are built on FHDL and provide various tools such as a system-on-chip interconnect infrastructure, a dataflow programming system, a more traditional high-level synthesizer that compiles Python routines into state machines with datapaths, and a simulator that allows test benches to be written in Python.
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Migen is the foundation for MiSoC.
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{% end %}
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{% layoutlr1() %}
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<div class="col-12 col-md-8 mx-auto">
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{% layout_centered_content(min_width=true, force_left=true, card=true) %}
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<p class="mt-5">Other Migen libraries are built on FHDL and provide various tools such as a system-on-chip interconnect infrastructure, a dataflow programming system, a more traditional high-level synthesizer that compiles Python routines into state machines with datapaths, and a simulator that allows test benches to be written in Python.</p>
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##### More...
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<p>Migen is the foundation for MiSoC.</p>
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You can find the Migen source <a href="http://github.com/m-labs/migen" target="_blank" rel="noopener noreferrer">here</a>, released under the permissive BSD license.
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</div>
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**Documentation** (note: sometimes out of date - please help!)
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<div class="col-12 col-md-8 mx-auto my-5">
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<div class="card shadow py-4 px-3">
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<h5 class="mb-1">More...</h5>
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<p>You can find the Migen source <a href="http://github.com/m-labs/migen" target="_blank" rel="noopener noreferrer">here</a>, released under the permissive BSD license.</p>
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<p class="mb-1"><strong>Documentation</strong> (note: sometimes out of date - please help!)</p>
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<ul class="ml-0 mb-0 th">
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<li class="pt-2 pb-2"><a href="https://m-labs.hk/migen/manual" target="_blank" rel="noopener noreferrer">User guide</a></li>
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<li class="pt-2 pb-2"><a href="https://m-labs.hk/migen/tutorial.pdf" target="_blank" rel="noopener noreferrer">Tutorial: An introduction to Migen</a></li>
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<li class="pt-2 pb-2"><a href="https://m-labs.hk/migen/slides.pdf" target="_blank" rel="noopener noreferrer">Lecture slides</a></li>
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<li class="pt-2 pb-2"><a href="https://www.wdj-consulting.com/blog/migen-port.html" target="_blank" rel="noopener noreferrer">Tutorial "Porting a New Board To Migen"</a> by cr1901</li>
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<li class="pt-2 pb-2"><a href="https://lab.whitequark.org/notes/2016-10-18/implementing-an-uart-in-verilog-and-migen/" target="_blank" rel="noopener noreferrer">"Implementing a UART in Verilog and Migen"</a> by whitequark</li>
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<li class="pt-2 pb-2"><a href="https://lab.whitequark.org/notes/2016-10-19/implementing-a-simple-soc-in-migen/" target="_blank" rel="noopener noreferrer">"Implementing a simple SoC in Migen"</a> by whitequark</li>
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<li class="pt-2 pb-2"><a href="http://blog.lambdaconcept.com/doku.php?id=migen:tutorial" target="_blank" rel="noopener noreferrer">Migen Step by Step Tutorial</a> by LambdaConcept</li>
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</ul>
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</div>
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</div>
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{% end %}
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{% layoutlr1() %}
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<div class="col-12 col-md-6">
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<h5 class="mb-1">MiSoC</h5>
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<p>Built on Migen, MiSoC provides a high performance, flexible and lightweight solution to build system-on-chips for various applications.</p>
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<ul class="ml-0 th">
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<li class="pt-2 pb-2">
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CPU options:
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<ul>
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<li class="pt-2 pb-2">LatticeMico32, modified to include an optional MMU (experimental).</li>
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<li class="pt-2 pb-2">mor1kx, a better OpenRISC implementation.</li>
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</ul>
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</li>
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<li class="pt-2 pb-2">Memory controller supports SDR, DDR, LPDDR, DDR2 and DDR3.</li>
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<li class="pt-2 pb-2">Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI flash controller, Ethernet MAC, and more.</li>
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<li class="pt-2 pb-2">High performance: on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR SDRAM bandwidth, 1080p 32bpp framebuffer, etc.</li>
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<li class="pt-2 pb-2">Low resource usage: basic implementation fits easily in Spartan-6 LX9.</li>
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<li class="pt-2 pb-2">Portable and easy to customize thanks to Python- and Migen-based architecture.</li>
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<li class="pt-2 pb-2">Design new peripherals using Migen and benefit from automatic CSR maps and logic, simplified DMAs, etc.</li>
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<li class="pt-2 pb-2">Possibility to encapsulate legacy Verilog/VHDL code.</li>
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</ul>
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<p>The MiSoC source is <a href="http://github.com/m-labs/misoc" target="_blank" rel="noopener noreferrer">here</a>, mostly covered by the permissive BSD license.</p>
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</div>
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<div class="d-none d-md-block col-md-6">
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<img src="/images/side-graphic-min.png">
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</div>
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- <a href="https://m-labs.hk/migen/manual" target="_blank" rel="noopener noreferrer">User guide
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- <a href="https://m-labs.hk/migen/tutorial.pdf" target="_blank" rel="noopener noreferrer">Tutorial: An introduction to Migen
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- <a href="https://m-labs.hk/migen/slides.pdf" target="_blank" rel="noopener noreferrer">Lecture slides
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- <a href="https://www.wdj-consulting.com/blog/migen-port.html" target="_blank" rel="noopener noreferrer">Tutorial "Porting a New Board To Migen"</a> by cr1901
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- <a href="https://lab.whitequark.org/notes/2016-10-18/implementing-an-uart-in-verilog-and-migen/" target="_blank" rel="noopener noreferrer">"Implementing a UART in Verilog and Migen"</a> by whitequark
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- <a href="https://lab.whitequark.org/notes/2016-10-19/implementing-a-simple-soc-in-migen/" target="_blank" rel="noopener noreferrer">"Implementing a simple SoC in Migen"</a> by whitequark
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- <a href="http://blog.lambdaconcept.com/doku.php?id=migen:tutorial" target="_blank" rel="noopener noreferrer">Migen Step by Step Tutorial</a> by LambdaConcept
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{% end %}
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{% layout_text_img(src="images/side-graphic-min.png", alt="", textleft=true, shadow=false) %}
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##### MiSoC
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Built on Migen, MiSoC provides a high performance, flexible and lightweight solution to build system-on-chips for various applications.
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- CPU options:
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- LatticeMico32, modified to include an optional MMU (experimental).
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- mor1kx, a better OpenRISC implementation.
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- Memory controller supports SDR, DDR, LPDDR, DDR2 and DDR3.
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- Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI flash controller, Ethernet MAC, and more.
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- High performance: on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
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- Low resource usage: basic implementation fits easily in Spartan-6 LX9.
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- Portable and easy to customize thanks to Python- and Migen-based architecture.
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- Design new peripherals using Migen and benefit from automatic CSR maps and logic, simplified DMAs, etc.
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- Possibility to encapsulate legacy Verilog/VHDL code.
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{% end %}
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@ -1,8 +1,14 @@
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<div class="{% if css %}{{ css }}{% else %}row d-flex align-items-center mt-5 mb-5{% endif %}">
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<div class="{% if min_width %}col-12 col-md-8 mx-auto{% else %}col-12{% endif %} text-center">
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<div class="{% if min_width %}col-12 col-md-8 mx-auto{% else %}col-12{% endif %} {% if not force_left %}text-center{% endif %}">
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{% if card %}
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<div class="card shadow py-4 px-3">
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{{ body | markdown | safe }}
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</div>
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{% else %}
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{{ body | markdown | safe }}
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{% endif %}
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</div>
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