Merge branch 'master' of https://git.m-labs.hk/M-Labs/web2019

content/about-us/jobs.md

@@ -0,0 +1,20 @@
++++
+title = "Jobs"
+weight = 1
+template = "page.html"
++++
+
+
+{% layout_centered_content(force_left=true, min_width=true) %}
+
+We are looking for talented people to join our team. If you want to be at the intersection of physics and engineering, collaborate with world-class scientists, and have the freedom to work with cutting-edge open source technology such as embedded Rust, LLVM, and next-generation FPGA tools such as the nMigen language and Yosys - then consider a job at M-Labs.
+
+Our office is located in the center of Hong Kong, a cosmopolitan city with world-class infrastructure, many cultural and social events, and <a href="https://www.discoverhongkong.com/eng/see-do/great-outdoors/hikes/index.jsp" rel="noopener noreferrer" target="_blank">beautiful natural scenery</a>. It has a separate system from mainland China, where, for example, communications are unrestricted, taxes are low, and customs tariffs virtually inexistent. Hong Kong is located next to Shenzhen, a city with <a href="https://www.wired.co.uk/video/shenzhen-full-documentary" rel="noopener noreferrer" target="_blank">a bustling tech scene</a>, and where many of the world's electronic gadgets are designed and manufactured.
+
+For local applicants, now is your chance to work on top-notch science and technology projects with partners worldwide, including Oxford University and <a href="https://www.nist.gov/nist-and-nobel/dave-wineland" rel="noopener noreferrer" target="_blank">NIST</a> - in <a href="https://web.archive.org/web/20170114210545/https://www.nature.com/articles/s41570-016-0001" rel="noopener noreferrer" target="_blank">a field whose applications are responsible for 20% of GDP</a>. For international applicants, Hong Kong provides <a href="https://www.immd.gov.hk/eng/services/visas/GEP.html" rel="noopener noreferrer" target="_blank">fast</a>, <a href="https://www.immd.gov.hk/eng/services/fee-tables/index.html" rel="noopener noreferrer" target="_blank">low-cost</a>, and relatively hassle-free employment visa processing.<br />
+
+We also accept remote positions, and you may also choose to work at our sister company QUARTIQ GmbH in Berlin-Adlershof, Germany.
+
+Contact us at jobs@m-****.hk!
+
+{% end %}

content/experiment-control/control-loops.md

@@ -7,9 +7,9 @@ template = "page.html"
 
 {% layout_text_img(src="images/stabilizer@2x.png", popup="images/origin/stabilizer.jpg", alt="", textleft=true, shadow=false) %}
 
-##### Stabilizer
+##### Sinara 8452 DSP "Stabilizer"
 
-The stabilizer module is a CPU-based dual-channel fast servo. It can be controlled by Kasli or work stand-alone with Power-over-Ethernet (PoE) supply.
+The Sinara 8452 DSP is a CPU-based dual-channel digital signal processing platform, particularly suited to fast servo applications. It can be controlled by Kasli or work stand-alone with Power-over-Ethernet (PoE) supply.
 
 - 400MHz STM32H743ZIT6
 - dual 16bit ADC with x2, x5, x10 PGA (2MS/s)
@@ -72,9 +72,9 @@ The <a href="https://github.com/quartiq/stabilizer" target="_blank" rel="noopene
 
 {% layout_text_img(src="images/Thermostat@2x.png", popup="images/origin/thermostat.jpg", alt="", shadow=false) %}
 
-##### Thermostat
+##### Sinara 8451 Thermostat
 
-This module is a 2-channel temperature controller EEM based on the Maxim MAX1968 driver, capable of driving 6W into a TEC or resistive heater. The sensor interface is based on AD7172 ADC.
+The Sinara 8451 Thermostat is a 2-channel temperature controller EEM based on the Maxim MAX1968 driver, capable of driving 6W into a TEC or resistive heater. The sensor interface is based on AD7172 ADC.
 
 Preliminary specifications:
 
@@ -97,8 +97,8 @@ This module is still in development and is not currently available.
 
 ##### SU-Servo
 
-With the SU-Servo feature of ARTIQ, the AD9910 variant of Urukul (which has fine amplitude control) can be used in combination with the Sampler ADC to form a laser intensity servo. In this application, the Urukul card drives AOMs and photodiodes are connected to Sampler to monitor laser intensities. When ordering your system, specify that you want SU-Servo integrated into the gateware.
+With the SU-Servo feature of ARTIQ, the Sinara 4410 DDS (which has fine amplitude control) can be used in combination with the 5108 Sampler to form a laser intensity servo. In this application, the 4410 DDS drives AOMs and photodiodes are connected to the 5108 Sampler to monitor laser intensities. When ordering your system, specify that you want SU-Servo integrated into the gateware.
 
-See the <a href="/experiment-control/sinara-core/">Sinara Core</a> page for the relevant devices (Kasli, Sampler and Urukul).
+See the <a href="/experiment-control/sinara-core/">Sinara Core</a> page for the relevant devices (1123 Processor "Kasli", 5108 Sampler, and 4410 DDS "Urukul").
 
-{% end %}
+{% end %}

content/experiment-control/resources.md

@@ -50,7 +50,7 @@ template = "page.html"
 
 
 
-{{ layout_separator(separator_title="Announcements, community support and discussions") }}
+{{ layout_separator(separator_title="Announcements, support and discussions") }}
 
 
 
@@ -116,3 +116,64 @@ We welcome inquiries from research groups of all sizes.<br><a href="https://gith
 
 </div>
 
+{{ layout_separator(separator_title="Community code") }}
+
+<div class="row">
+
+{% layout_card(title="Entangler core") %}
+<small>A FPGA core written in Migen with ARTIQ interface, for controlling remote quantum entanglement of trapped ions.</small>
+
+<a href="https://github.com/OxfordIonTrapGroup/entangler-core" target="_blank" rel="noopener noreferrer">Repository</a> | <a href="https://arxiv.org/abs/1911.10841" target="_blank" rel="noopener noreferrer">Paper</a>
+{% end %}
+
+
+{% layout_card(title="ndscan") %}
+<small>N-dimensional scans for ARTIQ</small>
+
+<a href="https://github.com/OxfordIonTrapGroup/ndscan" target="_blank" rel="noopener noreferrer">Repository</a>
+{% end %}
+
+
+{% layout_card(title="Oxford routines") %}
+<small>Oxford Ion-Trap Group routines</small>
+
+<a href="https://github.com/OxfordIonTrapGroup/oitg" target="_blank" rel="noopener noreferrer">Repository</a>
+{% end %}
+
+{% layout_card(title="Terminal interface") %}
+<small>A terminal interface for the Advanced Real-Time Infrastructure for Quantum physics (ARTIQ).</small>
+
+<a href="https://github.com/chase1635321/ARTIQ" target="_blank" rel="noopener noreferrer">Repository</a>
+{% end %}
+
+{% layout_card(title="ARTIQ-suservo") %}
+<small>A set of scripts for the ARTIQ suservo device.</small>
+
+<a href="https://github.com/chase1635321/ARTIQ-suservo" target="_blank" rel="noopener noreferrer">Repository</a>
+{% end %}
+
+{% layout_card(title="nvOS") %}
+<small>A quantum operating system built around ARTIQ and NV centers in diamond.</small>
+
+<a href="https://github.com/vontell/nvOS" target="_blank" rel="noopener noreferrer">Repository</a>
+{% end %}
+
+{% layout_card(title="Haeffner Lab routines") %}
+<small>Haeffner Lab (Berkeley) routines</small>
+
+<a href="https://github.com/HaeffnerLab/artiq-work-lattice" target="_blank" rel="noopener noreferrer">Repository</a>
+{% end %}
+
+{% layout_card(title="WIPM routines") %}
+<small>WIPM (CAS Wuhan) routines</small>
+
+<a href="https://github.com/GuanQunMu/IonTrap-WIPM" target="_blank" rel="noopener noreferrer">Repository</a>
+{% end %}
+
+
+</div>
+
+{% layout_div(css="col-12 text-center") %}
+Want your project listed here? Write to sb@m-l\*\*\*.hk.
+
+{% end %}

content/experiment-control/sinara-core.md

@@ -22,9 +22,9 @@ Kasli and EEMs can be ordered now. We can deliver a rack-mountable crate that co
 
 {% layout_text_img(src="images/kasli@2x.png", popup="images/origin/kasli.jpg", alt="", shadow=false) %}
 
-##### Kasli
+##### Sinara 1123 Processor "Kasli"
 
-One of the main devices in the Sinara family is the Kasli core device. It contains an Artix-7 100T FPGA, DDR3 SDRAM, three SFP connectors, and can control up to 8 daughtercards (Eurocard Extension Module, EEM). The Kasli and its EEMs are installed in one Eurocard 3U chassis. One SFP connector is used for a Gigabit Ethernet connection to your computer network.
+One of the main devices in the Sinara family is the 1123 Processor (codenamed Kasli). It contains an Artix-7 100T FPGA, DDR3 SDRAM, three SFP connectors, and can control up to 8 daughtercards (Eurocard Extension Module, EEM) or 12 with the "backplane adapter". The Kasli can act as a stand-alone core device, or as a DRTIO satellite or repeater. The Kasli and its EEMs are installed in one Eurocard 3U chassis. One SFP connector is used for a Gigabit Ethernet connection to your computer network.
 
 <a href="https://github.com/sinara-hw/Kasli/wiki" target="_blank" rel="noopener noreferrer">More information</a>
 
@@ -34,9 +34,9 @@ One of the main devices in the Sinara family is the Kasli core device. It contai
 
 {% layout_text_img(src="images/isolated-ttl@2x.png", popup="images/origin/dio.jpg", alt="", textleft=true, shadow=false) %}
 
-##### Isolated TTL I/O EEMs
+##### Sinara 2118/2128/2138 TTL cards
 
-For simple TTL signals, we offer I/O cards with 8 channels over BNC or SMA connectors in the EEM form factor. The IOs are divided into two banks of 4, with per-bank ground isolation. The direction (input/output) and termination (high-Z/50R) is selectable on a per-channel basis via I2C or on-board switches. Outputs can supply 5V into 25Ohm, and can tolerate an indefinite short-circuit to ground.
+For simple TTL signals, we offer I/O cards in the EEM form factor with 8 channels over BNC (2118), SMA (2128) or MCX (2138) connectors. The IOs are divided into two banks of 4, with per-bank ground isolation. The direction (input/output) and termination (high-Z/50R) is selectable on a per-channel basis via I2C or on-board switches. The open circuit voltage of outputs is 5V, and outputs can supply a valid TTL level into 50&#8486; and tolerate an indefinite short circuit to ground.
 
 More information: <a href="https://github.com/sinara-hw/DIO_BNC/wiki" target="_blank" rel="noopener noreferrer">BNC card</a> <a href="https://github.com/sinara-hw/DIO_SMA/wiki" target="_blank" rel="noopener noreferrer">SMA card</a>
 
@@ -46,10 +46,10 @@ More information: <a href="https://github.com/sinara-hw/DIO_BNC/wiki" target="_b
 
 {% layout_text_img(src="images/LVDS@2x.png", popup="images/origin/dio_rj45.jpg", alt="", shadow=false) %}
 
-##### LVDS I/O EEM
+##### Sinara 2245 LVDS TTL card
 
-For high-density or faster signals, DIO_RJ45 is an extension module supplying 16 LVDS pairs via 4 front-panel RJ45 connectors.
+For high-density or faster signals, the Sinara 2245 is an extension module supplying 16 LVDS pairs via 4 front-panel RJ45 connectors.
-Each RJ45 supplies 4 LVDS DIOs. The direction (input/output) is individually selectable for each signal via on-board switches. Outputs are intended to drive 100Ohm loads (LVDS is short-circuit protected), inputs are 100Ohm terminated. The connectors dedicate all 8 pins to LVDS signals, ground is on the connector shield so only shielded Ethernet cat 6 shielded cables are allowed.
+Each RJ45 supplies 4 LVDS DIOs. The direction (input/output) is individually selectable for each signal via on-board switches. Outputs are intended to drive 100&#8486; loads (LVDS is short-circuit protected), inputs are 100&#8486; terminated. The connectors dedicate all 8 pins to LVDS signals, ground is on the connector shield so only shielded Ethernet cat 6 shielded cables are allowed.
 
 <a href="https://github.com/sinara-hw/DIO_RJ45/wiki" target="_blank" rel="noopener noreferrer">More information</a>
 
@@ -59,9 +59,9 @@ Each RJ45 supplies 4 LVDS DIOs. The direction (input/output) is individually sel
 
 {% layout_text_img(src="images/Banker-TTL-1@2x.png", popup="images/origin/banker1.jpg", alt="", textleft=true, shadow=false) %}
 
-##### Banker 128-channel TTL I/O expander
+##### Sinara 3128 TTL I/O expander "Banker"
 
-Banker is a versatile 128 TTL GPIO module. It has flexible connectivity and contains a small Lattice iCE40 FPGA, supported by Yosys and IceStorm.
+Banker is a versatile 128-channel TTL GPIO module. It has flexible connectivity and contains a small Lattice iCE40 FPGA, supported by Yosys and IceStorm.
 Interfaces include:
 
 - 8 x 8 channel IDC connectors, compatible with BNC-IDC and SMA-IDC.
@@ -96,11 +96,11 @@ There are several DIN-rail compatible modules for use with Banker. They are inte
 
 {% layout_text_img(src="images/Urukul-DDS@2x.png", popup="images/origin/urukul.jpg", alt="", shadow=false) %}
 
-##### Urukul DDS card
+##### Sinara 4410/4412 DDS "Urukul"
 
-Urukul is a 4 channel DDS-based frequency synthesizer for the EEM form factor. It provides sub-Hz frequency resolution, controlled phase steps, and accurate output amplitude control. We offer it in two variants, with either the AD9910 or the AD9912 chip.
+Urukul is a 4 channel DDS-based frequency synthesizer for the EEM form factor. It provides sub-Hz frequency resolution, controlled phase steps, and accurate output amplitude control. We offer it in two variants, with either the AD9910 (Sinara 4410) or the AD9912 (Sinara 4412) chip.
 
-With the SU-Servo feature of ARTIQ, the AD9910 variant of Urukul (which has fine amplitude control) can be used in combination with the Sampler ADC to form a laser intensity servo. In this application, the Urukul card drives AOMs and photodiodes are connected to Sampler to monitor laser intensities. When ordering your system, specify that you want SU-Servo integrated into the gateware.
+With the SU-Servo feature of ARTIQ, the 4410 DDS (which has fine amplitude control, unlike the 4412) can be used in combination with the 5108 Sampler to form a laser intensity servo. In this application, the Urukul card drives AOMs and photodiodes are connected to Sampler to monitor laser intensities. When ordering your system, specify that you want SU-Servo integrated into the gateware.
 
 In regular mode, various DDS features are supported, including frequency, phase and amplitude control, and AD9910 RAM mode. See the ARTIQ manual for more details.
 
@@ -112,11 +112,11 @@ In regular mode, various DDS features are supported, including frequency, phase
 
 {% layout_text_img(src="images/Mirny-Synth@2x.png", popup="images/origin/mirny.jpg", alt="", textleft=true, shadow=false) %}
 
-##### Mirny PLL synthesizer card
+##### Sinara 4456 synthesizer "Mirny"
 
 Mirny is a 4 channel wide-band PLL/VCO-based microwave frequency synthesiser.
 
-Like the Urukul DDS Synthesiser but with a VCO/PLL (ADF5356) as the synthesizer and options for frequency double/tripler and analog frontend mezzanines.
+Like the Urukul DDS but with a VCO/PLL (ADF5356) as the synthesizer and options for frequency double/tripler and analog frontend mezzanines.
 
 Comparing Mirny to Urukul:
 
@@ -136,7 +136,7 @@ Comparing Mirny to Urukul:
 
 {% layout_text_img(src="images/Zotino-DAC@2x.png", popup="images/origin/zotino.jpg", alt="", shadow=false) %}
 
-##### Zotino DAC card
+##### Sinara 5432 DAC "Zotino"
 
 Zotino is a 32-channel, 16-bit DAC EEM with an update rate of 1MSPS (divided between the channels). It was designed for low noise and good stability.
 
@@ -146,17 +146,25 @@ It is also possible to connect the Zotino using a HD68 cable to an external crat
 
 <a href="https://github.com/sinara-hw/Zotino/wiki" target="_blank" rel="noopener noreferrer">More information</a>
 
+##### Sinara 5632 DAC "Fastino"
+
+Fastino is a higher-speed version of Zotino. It also has 32 16-bit channels, but they all can be updated at 2Msps simultaneously (1Gb/s data).
+
+Note that reaching this maximum hardware speed requires gateware acceleration; naively pushing samples one by one from a software ARTIQ-Python kernel results in a much lower update rate.
+
+<a href="https://github.com/sinara-hw/Fastino/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
 {% end %}
 
 
 
 {% layout_text_img(src="images/Sampler-ADC@2x.png", popup="images/origin/sampler.jpg", alt="", textleft=true, shadow=false) %}
 
-##### Sampler ADC card
+##### Sinara 5108 Sampler
 
-Sampler is an 8-channel, 16-bit ADC EEM with an update rate of up to 1.5MSPS (all channels simultaneously). It has low-noise differential front end with a digitally programmable gain, providing full-scale input ranges between +-10mV (G=1000) and +-10V (G=1).
+The Sinara 5108 is an 8-channel, 16-bit ADC EEM with an update rate of up to 1.5MSPS (all channels simultaneously). It has low-noise differential front end with a digitally programmable gain, providing full-scale input ranges between +-10mV (G=1000) and +-10V (G=1).
 
-In SU-Servo mode, Sampler can be used in combination with Urukul to form a laser intensity servo. Otherwise, in regular mode, single sample values can be read out by ARTIQ kernels (due to CPU overhead, the actual sample rate in regular mode is reduced).
+In SU-Servo mode, the 5108 Sampler can be used in combination with the 4410 DDS to form a laser intensity servo. Otherwise, in regular mode, single sample values can be read out by ARTIQ kernels (due to CPU overhead, the actual sample rate in regular mode is reduced).
 
 <a href="https://github.com/sinara-hw/Sampler/wiki" target="_blank" rel="noopener noreferrer">More information</a>
 
@@ -168,9 +176,9 @@ Note that update rate specification on this page is for the hardware only; ARTIQ
 
 {% layout_text_img(src="images/Grabber-camera-interface@2x.png", popup="images/origin/grabber.jpg", alt="", shadow=false) %}
 
-##### Grabber camera interface
+##### Sinara 6302 Grabber
 
-Grabber allows the connection of certain scientific (EM)CCD cameras port to the core FPGA. Those cameras have a Camera Link interface.
+The Sinara 6302 Grabber allows the connection of certain scientific (EM)CCD cameras port to the core FPGA. Those cameras have a Camera Link interface.
 
 In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on one rectangular pixel region and accumulates pixel values for each frame. The ROI engines operate independently and can be overlapping. After the frame, the accumulated value is pushed as an RTIO input event. Regions of interest (ROI) can be configured at runtime, and are defined with the computer.
 
@@ -182,9 +190,9 @@ In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on
 
 {% layout_text_img(src="images/clocker@2x.png", popup="images/origin/clocker.jpg", alt="", textleft=true, shadow=false) %}
 
-##### Clocker
+##### Sinara 7210 Clocker
 
-A low-noise clock distribution module that can be used to distribute low jitter clock signal among 3U boards. 2 inputs, 10 outputs including 4 SMAs, frequency up to 1GHz, low jitter <100fs RMS.
+The Sinara 7210 is a low-noise clock distribution module that can be used to distribute low jitter clock signal among 3U boards. 2 inputs, 10 outputs including 4 SMAs, frequency up to 1GHz, low jitter <100fs RMS.
 
 <a href="https://github.com/sinara-hw/Clocker/wiki" target="_blank" rel="noopener noreferrer">More information</a>
 

sass/css/_layout.scss

@@ -64,6 +64,14 @@
   padding-top: 81.64%;
 }
 
+.card-jobs {
+  background: #fff url("../images/jobs-phone@2x.png") no-repeat top center;
+  background-size: contain;
+}
+.card-jobs > div {
+  padding-top: 81.64%;
+}
+
 
 .card h5,
 h5 {
@@ -119,6 +127,10 @@ img.kf25 {
   .card-gateware > div {
     padding-top: 0;
   }
+
+  .card-jobs > div {
+    padding-top: 0;
+  }
 }
 
 // Medium devices (tablets, 768px and up)
@@ -207,6 +219,10 @@ img.kf25 {
     background: #fff url("../images/gateware@2x.png") no-repeat top right;
   }
 
+  .card-jobs {
+    background: #fff url("../images/jobs@2x.png") no-repeat center right;
+  }
+
   .logos-centered {
     p {
       img {

templates/index.html

@@ -96,6 +96,38 @@
 
     </div>
 
+    <div class="row pb-5">
+
+      <div class="col-12">
+
+        <div class="card shadow mt-3 mb-3">
+
+          <div class="card-body p-3 p-md-5 card-jobs">
+
+            <div class="col-12 col-md-6 pl-0 pr-0">
+
+              <h5 class="card-title">Jobs</h5>
+
+              <p class="card-text pt-3">
+                We are looking for talented people to join our team. If you want to be at the intersection of physics and engineering, collaborate with world-class scientists, and have the freedom to work with cutting-edge open source technology such as embedded Rust, LLVM, and next-generation FPGA tools such as the nMigen language and Yosys - then consider a job at M-Labs.
+              </p>
+              <p class="card-text pt-3"><small>
+                Our office is located in the center of Hong Kong, a cosmopolitan city with world-class infrastructure, many cultural and social events, and <a href="https://www.discoverhongkong.com/eng/see-do/great-outdoors/hikes/index.jsp" rel="noopener noreferrer" target="_blank">beautiful natural scenery</a>. It has a separate system from mainland China, where, for example, communications are unrestricted, taxes are low, and customs tariffs virtually inexistent. Hong Kong is located next to Shenzhen, a city with <a href="https://www.wired.co.uk/video/shenzhen-full-documentary" rel="noopener noreferrer" target="_blank">a bustling tech scene</a>, and where many of the world's electronic gadgets are designed and manufactured.<br />
+                For local applicants, now is your chance to work on top-notch science and technology projects with partners worldwide, including Oxford University and <a href="https://www.nist.gov/nist-and-nobel/dave-wineland" rel="noopener noreferrer" target="_blank">NIST</a> - in <a href="https://web.archive.org/web/20170114210545/https://www.nature.com/articles/s41570-016-0001" rel="noopener noreferrer" target="_blank">a field whose applications are responsible for 20% of GDP</a>. For international applicants, Hong Kong provides <a href="https://www.immd.gov.hk/eng/services/visas/GEP.html" rel="noopener noreferrer" target="_blank">fast</a>, <a href="https://www.immd.gov.hk/eng/services/fee-tables/index.html" rel="noopener noreferrer" target="_blank">low-cost</a>, and relatively hassle-free employment visa processing.<br />
+                We also accept remote positions, and you may also choose to work at our sister company QUARTIQ GmbH in Berlin-Adlershof, Germany.<br />
+                Contact us at jobs@m-****.hk!
+              </small></p>
+
+            </div>
+
+          </div>
+
+        </div>
+
+      </div>
+
+    </div>
+
 
     <div class="row pt-5 pb-5">