forked from sinara-hw/datasheets
299 lines
16 KiB
TeX
299 lines
16 KiB
TeX
\include{preamble.tex}
|
|
\graphicspath{{images/1124}{images}}
|
|
|
|
\title{1124 Carrier Kasli 2.0}
|
|
\author{M-Labs Limited}
|
|
\date{January 2022}
|
|
\revision{Revision 1}
|
|
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
|
|
\begin{document}
|
|
\maketitle
|
|
|
|
\section{Features}
|
|
|
|
\begin{itemize}
|
|
\item{4 SFP 6Gb/s slots for Ethernet or DRTIO.}
|
|
\item{12 EEM Connectors.}
|
|
\item{4 MMCX clock outputs.}
|
|
\item{FPGA core device.}
|
|
\end{itemize}
|
|
|
|
\section{Applications}
|
|
|
|
\begin{itemize}
|
|
\item{Runs ARTIQ kernels.}
|
|
\item{Control the EEMs.}
|
|
\item{Communication with the host.}
|
|
\end{itemize}
|
|
|
|
\section{General Description}
|
|
The 1124 Carrier Kasli 2.0 card is a 8hp EEM module.
|
|
It controls the EEMs by running ARTIQ kernels sent from the host.
|
|
|
|
It supports 12 EEM connections to other EEM cards in the ARTIQ Sinara family.
|
|
Real-time control of the EEMs are implemented using the RTIO system.
|
|
1ns temporal resolution can be achieved for TTL events.
|
|
|
|
4 SFP 6Gb/s slots are supported for Ethernet or DRTIO.
|
|
Communication with the host is supported by the Ethernet, while the
|
|
Distributed Real Time Input/Output (DRTIO) system allows inclusion of
|
|
additional core devices (e.g. Kasli 2.0) as DRTIO satellites,
|
|
indirectly controlled by the DRTIO Master.
|
|
|
|
% Switch to next column
|
|
\vfill\break
|
|
|
|
\begin{figure}[h]
|
|
\centering
|
|
\scalebox{1.15}{
|
|
\begin{circuitikz}[european, every label/.append style={align=center}]
|
|
|
|
\begin{scope}[]
|
|
|
|
% Draw the FPGA
|
|
\draw (0, 0) node[twoportshape, t={FPGA}, circuitikz/bipoles/twoport/height=1.5, circuitikz/bipoles/twoport/width=1.2, scale=1] (fpga) {};
|
|
|
|
% External clock for RTIO, west of the FPGA
|
|
\draw [color=white, text=black] (-3.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (ext_clk) {};
|
|
\node [label=left:\tiny{EXT CLK}] at (-2.65, 0) {};
|
|
\begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=-40cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\draw [-latexslim] (ext_clk) -- (fpga.west);
|
|
|
|
% USB Mirco B port with USB-UART converter, north west of the FPGA
|
|
\draw (-3.2, 1.2) node[twoportshape, t={USB Micro B}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (usb) {};
|
|
\draw (-2, 1.2) node[twoportshape, t={\fourcm{USB-UART}{Converter}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (uart) {};
|
|
\draw [latexslim-latexslim] (usb.north) -- (uart.south);
|
|
\draw [latexslim-latexslim] (uart.north) -- (-1.3, 1.2) -- (-1.3, 0.4) -- (-0.85, 0.4);
|
|
|
|
% 4-SFP cage, south west of the FPGA
|
|
\draw (-3.4, -0.8) node[twoportshape, t={SFP 0}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp0) {};
|
|
\draw (-3, -0.8) node[twoportshape, t={SFP 1}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp1) {};
|
|
\draw (-3.4, -1.5) node[twoportshape, t={SFP 2}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp2) {};
|
|
\draw (-3, -1.5) node[twoportshape, t={SFP 3}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp3) {};
|
|
\draw [latexslim-latexslim] (-2.8, -1.15) -- (-2.2, -1.15) -- (-2.2, -0.4) -- (-0.85, -0.4);
|
|
|
|
% Clock signal cleaning path, south of the FPGA,
|
|
% clock signal loop from the south west to the south east
|
|
\draw (-0.8, -2.1) node[twoportshape, t={\fourcm{Clock}{Multiplier}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_mul) {};
|
|
\draw (0.8, -2.1) node[twoportshape, t={\fourcm{Clock}{Buffer}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_buf) {};
|
|
\draw [-latexslim] (-0.85, -0.8) -- (-1.6, -0.8) -- (-1.6, -1.9) -- (-1.05, -1.9);
|
|
% % A dashed path from EXT CLK to CDR CLK
|
|
\draw [dashed, -latexslim] (fpga.west) -- (-0.6, 0) -- (-0.6, -0.8) -- (-0.85, -0.8);
|
|
% % Internal oscillator for the RTIO clock
|
|
\draw (-2.2, -2.3) node[twoportshape, t={OSC}, circuitikz/bipoles/twoport/width=1, scale=0.5] (rtio_osc) {};
|
|
\draw [-latexslim] (rtio_osc.east) -- (-1.05, -2.3);
|
|
\draw [-latexslim] (clk_mul.north) -- (clk_buf.south);
|
|
\draw [-latexslim] (clk_buf.north) -- (1.6, -2.1) -- (1.6, -0.4) -- (0.85, -0.4);
|
|
% % MMCX output
|
|
\draw [color=white, text=black] (2.75, -1.05) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx0) {};
|
|
\draw [color=white, text=black] (2.75, -1.4) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx1) {};
|
|
\draw [color=white, text=black] (2.75, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx2) {};
|
|
\draw [color=white, text=black] (2.75, -2.1) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx3) {};
|
|
\node [label=right:\tiny{MMCX 0}] at (2.3, -1.05) {};
|
|
\node [label=right:\tiny{MMCX 1}] at (2.3, -1.4) {};
|
|
\node [label=right:\tiny{MMCX 2}] at (2.3, -1.75) {};
|
|
\node [label=right:\tiny{MMCX 3}] at (2.3, -2.1) {};
|
|
\begin{scope}[scale=0.07 , rotate=90, xshift=-30cm, yshift=-35cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=90, xshift=-25cm, yshift=-35cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=90, xshift=-20cm, yshift=-35cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=90, xshift=-15cm, yshift=-35cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
|
|
\draw [-latexslim] (1.6, -1.05) -- (mmcx0);
|
|
\draw [-latexslim] (1.6, -1.4) -- (mmcx1);
|
|
\draw [-latexslim] (1.6, -1.75) -- (mmcx2);
|
|
\draw [-latexslim] (1.6, -2.1) -- (mmcx3);
|
|
|
|
% Memory modules, north of the FPGA
|
|
\draw (-0.55, 2.4) node[twoportshape, t={\fourcm{SPI}{Flash}}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (spi_flash) {};
|
|
\draw (0.55, 2.4) node[twoportshape, t={SDRAM}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (sdram) {};
|
|
\draw [latexslim-latexslim] (spi_flash.south) -- (-0.55, 1.05);
|
|
\draw [latexslim-latexslim] (sdram.south) -- (0.55, 1.05);
|
|
|
|
% EEM connectors x12, horizontally located at y=0.4
|
|
\draw (2, 1.8) node[twoportshape, t={EEM Port 0}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eem0) {};
|
|
\node at (2.4, 1.8)[circle,fill,inner sep=0.7pt]{};
|
|
\node at (2.6, 1.8)[circle,fill,inner sep=0.7pt]{};
|
|
\node at (2.8, 1.8)[circle,fill,inner sep=0.7pt]{};
|
|
\draw (3.2, 1.8) node[twoportshape, t={EEM Port 11}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eem11) {};
|
|
\draw [decorate, decoration = {brace}] (3.4, 1.1) -- (1.8, 1.1);
|
|
\draw [latexslim-latexslim] (2.6, 1) -- (2.6, 0.4) -- (0.85, 0.4);
|
|
\end{scope}
|
|
\end{circuitikz}
|
|
}
|
|
|
|
\caption{Simplified Block Diagram}
|
|
\end{figure}
|
|
|
|
\begin{figure}[hbt!]
|
|
\centering
|
|
\includegraphics[height=2in]{Kasli_FP.pdf}
|
|
\includegraphics[height=2in]{photo1124.jpg}
|
|
\caption{Kasli 2.0 Card photo}
|
|
\end{figure}
|
|
|
|
% For wide tables, a single column layout is better. It can be switched
|
|
% page-by-page.
|
|
\onecolumn
|
|
|
|
\section{Electrical Specifications}
|
|
External clock parameters are derived based on the internal termination specified in UG471\footnote{\label{ug471}https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO},
|
|
and the voltage range specified in DS181\footnote{\label{ds181}https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}.
|
|
The figure had accounted for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}).
|
|
\begin{table}[h]
|
|
\centering
|
|
\begin{threeparttable}
|
|
\caption{Recommended Operating Conditions}
|
|
\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
|
|
\thickhline
|
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
|
\textbf{Unit} & \textbf{Conditions} \\
|
|
\hline
|
|
Clock input & & & & &\\
|
|
\hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
|
|
\cline{2-6}
|
|
% 100R termination & 100/350/600 mV differential input after the transformer.
|
|
& \multicolumn{4}{c|}{10/100/125 MHz} & RTIO clock synthesized from input \\
|
|
\cline{2-6}
|
|
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
|
|
\hline
|
|
Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
|
|
\thickhline
|
|
\end{tabularx}
|
|
\end{threeparttable}
|
|
\end{table}
|
|
|
|
\section{Distributed RTIO (DRTIO)}
|
|
DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central core device.
|
|
Multiple core devices (e.g. Kasli 2.0) can be interconnected through DRTIO. All core devices in the DRTIO system are classified as 1 of the 2 roles:
|
|
\begin{enumerate}
|
|
\item DRTIO Master \\
|
|
The DRTIO master is unique in a DRTIO system. It controls the DRTIO satellites(s) and local RTIO channels.
|
|
\item DRTIO Satellite \\
|
|
The rest of the core devices are DRTIO satellites. DRTIO satellites need an upstream connection to one other core devices (master or satellite).
|
|
It may provide downstream conenction to other DRTIO satellties.
|
|
\end{enumerate}
|
|
|
|
|
|
\section{Network Interface}
|
|
Communication between the host and the core device(s) is implemented using small form-factor pluggable (SFP) interfaces.
|
|
Approprate SFP transceivers must be plugged inside the corresponding SFP cages to enable communication between core devices.
|
|
|
|
\subsection{Upstream Connection}
|
|
A core device (e.g. Kasli 2.0) must acquire an upstream network connection through the \texttt{SFP0} slot.
|
|
\begin{itemize}
|
|
\item Standalone/DRTIO master \\
|
|
An Ethernet capable SFP transceiver must be inserted to the \texttt{SFP0} slot.
|
|
Typically, a RJ45 SFP module is inserted to the slot with an Ethernet cable with network connection attached to the module.
|
|
\item DRTIO Satellite \\
|
|
The \texttt{SFP0} port of DRTIO satellite should be connected to an appropriate SFP slot of the upstream core device (DRTIO master or satellite) with cable connection with SFP transceivers.
|
|
\end{itemize}
|
|
|
|
\subsection{Downstream Connection}
|
|
The 1124 Carrier Kasli 2.0 supports up to 3 DRTIO satellite connections per device.
|
|
DRTIO satellites can be connected using any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) through cable connections with SFP transceivers.
|
|
|
|
\section{Clock Routing}
|
|
\subsection{DRTIO Master/Standalone}
|
|
The RTIO clock is typically synthesized by the Si5324 clock multiplier, and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors.
|
|
An external reference can be supplied to synthesize the clock, which is supplied to the SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis.
|
|
Kasli 2.0 supports a set of clock systhesizing options for the (D)RTIO system:
|
|
\begin{table}[H]
|
|
\centering
|
|
\begin{tabular}{|c|c|c|}
|
|
\hline
|
|
RTIO frequency & Configuration & Clock generation \\ \hline
|
|
100 MHz & \texttt{int\char`_100} & internal crystal oscillator using PLL, 100 MHz output \\ \hline
|
|
\multirow{4}{*}{125 MHz} & \texttt{int\char`_125} & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
|
|
& \texttt{ext0\char`_synth0\char`_10to125} & external 10 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
|
|
& \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output \\ \cline{2-3}
|
|
& \texttt{ext0\char`_synth0\char`_125to125} & external 125 MHz reference using PLL, 125 MHz output \\ \hline
|
|
150 MHz & \texttt{int\char`_150} & internal crystal oscillator using PLL, 150 MHz output \\ \hline
|
|
\end{tabular}
|
|
\end{table}
|
|
Alternatively, the clock synthesizer can be bypassed using the \texttt{ext0\char`_bypass} clocking option, where the RTIO clock is directly supplied to the SMA connector.
|
|
The resulting clock signal is then routed to both the RTIO system and downstream DRTIO satellites.
|
|
|
|
Clocking options should be configured by setting the value of the \texttt{rtio} key to the desired configuration through \texttt{artiq\char`_coremgmt}.
|
|
For example, the RTIO frequency is synthesized from the external 10 MHz from the SMA connector after issuing the following command.
|
|
\begin{minted}{bash}
|
|
artiq_coremgmt config write -s rtio ext0_synth0_10to125
|
|
\end{minted}
|
|
|
|
\subsection{DRTIO Satellite}
|
|
The RTIO clock is first recovered from the SFP transceiver connected to the upstream device. The signal is then cleaned by Si5324 clock synthesizer.
|
|
The resulting clock signal is then routed to the RTIO system and downstream DRTIO satellties.
|
|
|
|
\newpage
|
|
|
|
\section{Example ARTIQ code}
|
|
The sections below demonstrate simple usage scenarios of the system extensions of the ARTIQ control system.
|
|
These extensions make use of the resources on 1124 Carrier Kasli 2.0.
|
|
They do not exhaustively demonstrate all the features of the ARTIQ system.
|
|
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
|
|
|
|
\subsection{Direct Memory Access (DMA)}
|
|
Instead of directly emitting RTIO events, a sequence of RTIO events can be recorded in advance and stored in the local SDRAM.
|
|
The event sequence can be replayed at another specified timestamp at a higher speed compared to the CPU alone.
|
|
The following example records an LED blinking sequence, and replayed twice consecutively using \texttt{CoreDMA}.
|
|
\texttt{led0} blinked twice in this example.
|
|
|
|
\inputcolorboxminted{firstline=10,lastline=29}{examples/dma.py}
|
|
|
|
The stored waveform can be referenced and replayed in different kernels.
|
|
However, the waveform is no longer retrievable once core device is rebooted.
|
|
|
|
\newpage
|
|
|
|
\subsection{Dataset Manipulation with Core Device Cache}
|
|
Experiments may require values computed/found in previously executed kernels.
|
|
To avoid invoking an RPC/sacrificing the pre-computation in \texttt{prepare()} stage, data can be cached in the core device cache.
|
|
The following code snippets consists of 2 experiments, where the data from the first experiement is cached.
|
|
The same data is retrieved and printed as hexadecimal in the second experiment.
|
|
|
|
\inputcolorboxminted{firstline=9,lastline=16}{examples/cache.py}
|
|
\inputcolorboxminted{firstline=24,lastline=35}{examples/cache.py}
|
|
|
|
Similar to DMA, the cached data is no longer retrievable once the core device is rebooted.
|
|
|
|
\section{Ordering Information}
|
|
To order, please visit \url{https://m-labs.hk} and select the 1124 Carrier Kasli 2.0 in the ARTIQ Sinara crate configuration tool.
|
|
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
|
|
|
|
\section*{}
|
|
\vspace*{\fill}
|
|
|
|
\input{footnote.tex}
|
|
|
|
\end{document}
|