forked from sinara-hw/datasheets
151 lines
4.6 KiB
Python
151 lines
4.6 KiB
Python
from artiq.experiment import *
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class OnePulsePerSecond(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.ttl0 = self.get_device("ttl0")
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@kernel
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def run(self):
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self.core.reset()
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while True:
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self.ttl0.pulse(500*ms)
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delay(500*ms)
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class MorseCode(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.led = self.get_device("led0")
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def prepare(self):
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# As of ARTIQ-6, the ARTIQ compiler has limited string handling
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# capabilities, so we pass a list of integers instead.
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message = ".- .-. - .. --.-"
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self.commands = [{".": 1, "-": 2, " ": 3}[c] for c in message]
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@kernel
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def run(self):
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self.core.reset()
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for cmd in self.commands:
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if cmd == 1:
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self.led.pulse(100*ms)
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delay(100*ms)
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if cmd == 2:
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self.led.pulse(300*ms)
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delay(100*ms)
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if cmd == 3:
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delay(700*ms)
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class SoftwareEdgeCount(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.ttl0 = self.get_device("ttl0")
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@kernel
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def run(self):
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self.core.reset()
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gate_end_mu = self.ttl0.gate_rising(1*ms)
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counts = self.ttl0.count(gate_end_mu)
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print(counts)
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class EdgeCounter(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.edgecounter0 = self.get_device("ttl0_counter")
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@kernel
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def run(self):
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self.core.reset()
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self.edgecounter0.gate_rising(1*ms)
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counts = self.edgecounter0.fetch_count()
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print(counts)
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class ExternalTrigger(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.ttlin = self.get_device("ttl0")
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self.ttlout = self.get_device("ttl4")
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@kernel
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def run(self):
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self.core.reset()
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gate_end_mu = self.ttlin.gate_rising(5*ms)
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timestamp_mu = self.ttlin.timestamp_mu(gate_end_mu)
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at_mu(timestamp_mu + self.core.seconds_to_mu(10*ms))
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self.ttlout.pulse(1*us)
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class ShortPulse(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.ttl0 = self.get_device("ttl0")
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@kernel
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def run(self):
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self.core.reset()
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delay(6*ns) # Coarse RTIO period: 0 - 7 ns
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self.ttl0.pulse(3*ns) # Coarse RTIO period: 8 - 15 ns
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class ClockGen(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.ttl0 = self.get_device("ttl0")
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@kernel
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def run(self):
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self.core.reset()
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self.ttl0.set(62.5*MHz)
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from artiq.coredevice import spi2 as spi
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SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
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0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY |
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0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
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0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
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CLK_DIV = 125
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class SPIWrite(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.spi = self.get_device("dio_spi0")
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@kernel
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def run(self):
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self.core.reset()
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self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110)
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self.spi.write(0x13 << 24) # Shift the bits to the MSBs.
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# Since SPI_LSB_FIRST is NOT set,
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# SPI Machine will shift out bits from
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# the MSB of the `data` register.`
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self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110)
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self.spi.write(0xDEADBEEF)
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class SPIRead(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.spi = self.get_device("dio_spi0")
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@kernel
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def run(self):
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self.core.reset()
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self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001)
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self.spi.write(0x81 << 24) # Shift the bits to the MSBs.
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# Since SPI_LSB_FIRST is NOT set,
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# SPI Machine will shift out bits from
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# the MSB of the `data` register.`
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self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, CLK_DIV, 0b001)
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self.spi.write(0) # write() performs the SPI transfer.
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# As suggested by the timing diagram,
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# the exact value of this argument
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# does not matter.
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print(self.spi.read())
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