forked from sinara-hw/datasheets
434 lines
19 KiB
TeX
434 lines
19 KiB
TeX
\input{preamble.tex}
|
|
\graphicspath{{images/4456}{images}}
|
|
|
|
\title{4456 Synthesizer Mirny}
|
|
\author{M-Labs Limited}
|
|
\date{January 2022}
|
|
\revision{Revision 1}
|
|
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
|
|
|
|
\begin{document}
|
|
\maketitle
|
|
|
|
\section{Features}
|
|
|
|
\begin{itemize}
|
|
\item{4-channel VCO/PLL}
|
|
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz}
|
|
\item{Up to 13.6 GHz with Almazny mezzanine}
|
|
\item{Higher frequency resolution than Urukul}
|
|
\item{Lower jitter and phase noise}
|
|
\item{Large frequency changes take several milliseconds}
|
|
\end{itemize}
|
|
|
|
\section{Applications}
|
|
|
|
\begin{itemize}
|
|
\item{Low-noise microwave source}
|
|
\item{Quantum state control}
|
|
\item{Driving acousto/electro-optic modulators}
|
|
\end{itemize}
|
|
|
|
\section{General Description}
|
|
The 4456 Synthesizer Mirny card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
|
|
|
|
It provides 4 channels of PLL frequency synthesis. Output frequencies from 53 MHz to \textgreater 4 GHz are supported.The range can be expanded up to 13.6 GHz with the Almazny mezzanine (4467 HF Synthesizer).
|
|
|
|
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provides at least 50 dB isolation.
|
|
|
|
|
|
% Switch to next column
|
|
\vfill\break
|
|
|
|
\begin{figure}[h]
|
|
\centering
|
|
\scalebox{0.95}{
|
|
\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
|
|
|
|
\begin{scope}[]
|
|
|
|
% Node to pin-point the locations of SMA symbols
|
|
\draw[color=white, text=black] (-0.1, 0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (ext_clk) {};
|
|
\draw[color=white, text=black] (-0.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx) {};
|
|
\draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf0) {};
|
|
\draw[color=white, text=black] (-0.1, -2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf1) {};
|
|
\draw[color=white, text=black] (-0.1, -3.15) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf2) {};
|
|
\draw[color=white, text=black] (-0.1, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf3) {};
|
|
|
|
% Node to pin-point the locations of SMP symbols
|
|
\draw[color=white, text=black] (2.65, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (smp0) {};
|
|
\draw[color=white, text=black] (2.65, -2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (smp1) {};
|
|
\draw[color=white, text=black] (2.65, -3.15) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (smp2) {};
|
|
\draw[color=white, text=black] (2.65, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (smp3) {};
|
|
|
|
% Extra node to expand the future channel dotted area eastward
|
|
\draw[color=white, text=black] (2.1, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=0.4, scale=0.4 ] (sig3_east) {};
|
|
|
|
% Labels for female EXT_CLK, MMCX, RF {0, 1, 2, 3}
|
|
\node [label=left:\tiny{EXT CLK}] at (0.35, 0.35) {};
|
|
\node [label=left:\tiny{MMCX}] at (0.35, 0) {};
|
|
\node [label=left:\tiny{RF 0}] at (0.35, -1.75) {};
|
|
\node [label=left:\tiny{RF 1}] at (0.35, -2.45) {};
|
|
\node [label=left:\tiny{RF 2}] at (0.35, -3.15) {};
|
|
\node [label=left:\tiny{RF 3}] at (0.35, -3.85) {};
|
|
|
|
% draw female EXT_CLK, MMCX, RF {0, 1, 2, 3}
|
|
\begin{scope}[scale=0.07 , rotate=-90, xshift=-5cm, yshift=2cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=-90, xshift=25cm, yshift=2cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=-90, xshift=35cm, yshift=2cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=-90, xshift=45cm, yshift=2cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=-90, xshift=55cm, yshift=2cm]
|
|
\draw (0,0.65) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\clip (-0.8,0) rectangle (0.8,0.8);
|
|
\draw (0,0) circle(0.8);
|
|
\end{scope}
|
|
|
|
% draw female SMP connectors
|
|
\begin{scope}[scale=0.07 , rotate=90, xshift=-25cm, yshift=-45cm]
|
|
\draw (0,0) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=90, xshift=-35cm, yshift=-45cm]
|
|
\draw (0,0) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=90, xshift=-45cm, yshift=-45cm]
|
|
\draw (0,0) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\end{scope}
|
|
\begin{scope}[scale=0.07 , rotate=90, xshift=-55cm, yshift=-45cm]
|
|
\draw (0,0) -- (0,3);
|
|
\clip (-1.5,0) rectangle (1.5,1.5);
|
|
\draw (0,0) circle(1.5);
|
|
\end{scope}
|
|
|
|
% Labels for female SMP {0, 1, 2, 3}
|
|
\node [label=right:\tiny{SMP 0}] at (3, -1.75) {};
|
|
\node [label=right:\tiny{SMP 1}] at (3, -2.45) {};
|
|
\node [label=right:\tiny{SMP 2}] at (3, -3.15) {};
|
|
\node [label=right:\tiny{SMP 3}] at (3, -3.85) {};
|
|
|
|
% Draw the internal oscillator
|
|
\draw (0.02, -0.45) node[twoportshape, t={OSC}, circuitikz/bipoles/twoport/width=0.8, scale=0.4] (xo) {};
|
|
|
|
% Draw the clock buffers
|
|
\draw (1.6, 0) node[twoportshape, t={CLK Buffers}, circuitikz/bipoles/twoport/width=2.2, scale=0.5, rotate=-90] (clk_buf) {};
|
|
|
|
% Connect CLK_IN to PLL clock buffers
|
|
\draw [-latexslim] (ext_clk.east) -- (1.35, 0.35);
|
|
\draw [-latexslim] (mmcx.east) -- (1.35, 0);
|
|
\draw [-latexslim] (xo.east) -- (1.35, -0.45);
|
|
|
|
% Connect CPLD clk_sel to PLL clock buffers
|
|
\draw [-latexslim] (clk_buf.east) -- (1.6, -1.35);
|
|
|
|
% Signal path: From control signals / clock of PLL to output of the RF switches
|
|
\draw (1.6, -1.75) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig0) {};
|
|
\draw (1.6, -2.45) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig1) {};
|
|
\draw (1.6, -3.15) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig2) {};
|
|
\draw (1.6, -3.85) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig3) {};
|
|
|
|
% Connect RF to PLL block
|
|
\draw [latexslim-] (rf0.east) -- (sig0.west);
|
|
\draw [latexslim-] (rf1.east) -- (sig1.west);
|
|
\draw [latexslim-] (rf2.east) -- (sig2.west);
|
|
\draw [latexslim-] (rf3.east) -- (sig3.west);
|
|
|
|
% PLL signal path dotted area
|
|
\node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(rf3)(sig0)(sig3_east.east)] (abs_dds) {};
|
|
\node[fill=white, rotate=-90, scale=0.7] at (abs_dds.west) {PLL Channels};
|
|
|
|
% CPLD after signal path 0
|
|
\draw (4.6, -0.2) node[twoportshape, t={CPLD}, circuitikz/bipoles/twoport/width=1.1, scale=0.8, rotate=-90] (cpld) {};
|
|
|
|
% Connect CPLD to:
|
|
% PLL clock buffer
|
|
\draw [latexslim-] (clk_buf.north) -- (4.2, 0);
|
|
% PLL signal path
|
|
\draw [latexslim-latexslim] (4.2, -0.4) -- (2.2, -0.4) -- (2.2, -1.35);
|
|
|
|
% Connect each PLL channel to its cooresponding SMP connector
|
|
\draw [-latexslim] (sig0.east) -- (smp0.east);
|
|
\draw [-latexslim] (sig1.east) -- (smp1.east);
|
|
\draw [-latexslim] (sig2.east) -- (smp2.east);
|
|
\draw [-latexslim] (sig3.east) -- (smp3.east);
|
|
|
|
% Draw AFE header
|
|
\draw (4.6, -2.8) node[twoportshape, t={AFE Header}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (afe) {};
|
|
|
|
% Connect AFE header to CPLD
|
|
\draw [latexslim-latexslim] (cpld.east) -- (afe.west);
|
|
|
|
% Draw LVDS transceivers, EEM
|
|
\draw (6.2, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
|
|
\draw (6.2, -1.6) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
|
|
\draw (7.8, -1.5) node[twoportshape, t={EEM Port}, circuitikz/bipoles/twoport/width=3.8, scale=0.7, rotate=-90] (eem) {};
|
|
|
|
% Connect LVDS transceiver to CPLD
|
|
\draw [latexslim-latexslim] (lvds0.south) -- (5, 0);
|
|
\draw [latexslim-latexslim] (lvds1.south) -- (5.5, -1.6) -- (5.5, -0.4) -- (5, -0.4);
|
|
|
|
% Connect EEM to LVDS transceiver
|
|
\draw [latexslim-latexslim] (lvds0.north) -- (7.45, 0);
|
|
\draw [latexslim-latexslim] (lvds1.north) -- (7.45, -1.6);
|
|
|
|
% Draw EEPROM
|
|
\draw (6.2, -3.85) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (eeprom) {};
|
|
|
|
% Interconnect I2C between EEPROM, AFE header & EEM
|
|
\draw [latexslim-latexslim] (afe.north) -- (7.45, -2.8);
|
|
\draw [-latexslim] (6.2, -2.8) -- (eeprom.north);
|
|
|
|
\end{scope}
|
|
|
|
\end{circuitikz}
|
|
}
|
|
|
|
\caption{Simplified Block Diagram}
|
|
\end{figure}
|
|
|
|
\begin{figure}[h]
|
|
\centering
|
|
\scalebox{0.88}{
|
|
\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
|
|
|
|
\begin{scope}[]
|
|
% RF switches {0, 1, 2, 3} for SMA {0, 1, 2, 3}
|
|
\draw (1.4, 0) node[twoportshape, t={RF Switch}, circuitikz/bipoles/twoport/width=1.5, scale=0.6] (sw) {};
|
|
|
|
% Amplifiers {0, 1, 2, 3} for RF switches {0, 1, 2, 3}
|
|
\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
|
|
|
|
% Attenuators {0, 1, 2, 3} for amplifiers {0, 1, 2, 3}
|
|
\draw (4.6, 0) node[twoportshape, t=\fourcm{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
|
|
|
|
% PLL {0, 1, 2, 3} for attenuators {0, 1, 2, 3}
|
|
\draw (6.6, 0) node[twoportshape, t={PLL}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (pll) {};
|
|
|
|
% Connect main signal path
|
|
\draw [-latexslim] (pll.west) -- (att.north);
|
|
\draw [-latexslim] (att.south) -- (amp.west);
|
|
\draw [-latexslim] (amp.east) -- (sw.east);
|
|
|
|
% Connect abstract PLL clock input
|
|
\node [label=above:\tiny{CLK Buffers}] at (8, -0.2) {};
|
|
\draw [latexslim-] (pll.east) -- (8, 0);
|
|
|
|
% Insert CPLD signal to relevant components
|
|
\node [label=above:\tiny{CPLD}] at (8, 1.1) {};
|
|
\draw [-] (1.4, 1.3) -- (8, 1.3);
|
|
\draw [-latexslim] (1.4, 1.3) -- (sw.north);
|
|
\draw [-latexslim] (4.6, 1.3) -- (att.west);
|
|
\draw [-latexslim] (6.6, 1.3) -- (pll.north);
|
|
|
|
% Connect PLL to SMP connectors
|
|
\draw [-latexslim] (pll.south) -- (6.6, -1.35);
|
|
\node [label=below:\tiny{SMP}] at (6.6, -1.15) {};
|
|
|
|
% Direct the RF switch output to RF output
|
|
\draw [-latexslim] (sw.west) -- (0, 0);
|
|
\node [label=left:\tiny{RF}] at (0.2, 0) {};
|
|
|
|
\end{scope}
|
|
|
|
\end{circuitikz}
|
|
}
|
|
|
|
\caption{Simplified PLL Signal Path}
|
|
\end{figure}
|
|
|
|
\begin{figure}[hbt!]
|
|
\centering
|
|
\includegraphics[height=2in]{photo4456.jpg}
|
|
\includegraphics[height=3in, angle=90]{Mirny_FP.pdf}
|
|
\caption{Mirny card and front panel}
|
|
\end{figure}
|
|
|
|
% For wide tables, a single column layout is better. It can be switched
|
|
% page-by-page.
|
|
\onecolumn
|
|
|
|
\sourcesection{4456 Synthesizer Mirny}{https://github.com/sinara-hw/mirny}
|
|
|
|
\section{Electrical Specifications}
|
|
|
|
Specifications of parameters are based on the datasheets of the PLL IC
|
|
(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
|
|
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
|
|
and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
|
|
Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
|
|
|
|
\begin{table}[h]
|
|
\centering
|
|
\begin{threeparttable}
|
|
\caption{Recommended Operating Conditions}
|
|
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
|
\thickhline
|
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
|
\textbf{Unit} & \textbf{Conditions} \\
|
|
\hline
|
|
% Note to future editors, the clk_div signal in gateware is not used.
|
|
% Input divider was removed (mirny#8)
|
|
Clock input & & & & & \\
|
|
\hspace{3mm}Frequency\repeatfootnote{adf5356}
|
|
& 10 & & 250 & MHz & Single-ended clock input (PLL config.) \\
|
|
& 10 & & 600 & MHz & Differential clock input (PLL config.) \\
|
|
\cline{2-6}
|
|
\hspace{3mm}Differential input swing\repeatfootnote{clock_buffer}
|
|
& 0.11 & & 1.55 & V\textsubscript{p-p} & \\
|
|
\thickhline
|
|
\end{tabularx}
|
|
\end{threeparttable}
|
|
\end{table}
|
|
|
|
\begin{table}[h]
|
|
\centering
|
|
\begin{threeparttable}
|
|
\caption{Output Specifications}
|
|
\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
|
|
\thickhline
|
|
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
|
|
\textbf{Unit} & \textbf{Conditions} \\
|
|
\hline
|
|
Frequency & 53.125 & & 4000 & MHz & \\
|
|
\hline
|
|
Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
|
|
\hline
|
|
Resolution & \multicolumn{4}{c|}{} & \\
|
|
\hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{4}{c|}{52 bits} & \\
|
|
\hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{4}{c|}{24 bits} & \\
|
|
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{4}{c|}{0.5 dB} & \\
|
|
\thickhline
|
|
\end{tabularx}
|
|
\end{threeparttable}
|
|
\end{table}
|
|
|
|
\newpage
|
|
|
|
Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
|
|
|
|
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
|
|
\begin{itemize}
|
|
\item Red: Before any modifications
|
|
\item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
|
|
\end{itemize}
|
|
|
|
\begin{figure}[H]
|
|
\centering
|
|
\includegraphics[height=3in]{mirny_phase_noise_cm_choke.png}
|
|
\caption{Phase noise measurement at 1 GHz}
|
|
\end{figure}
|
|
|
|
Phase noise at different output frequencies is then measured:
|
|
|
|
\newcolumntype{Y}{>{\centering\arraybackslash}X}
|
|
|
|
\begin{table}[hbt!]
|
|
\centering
|
|
\begin{threeparttable}
|
|
\caption{Phase noise performance}
|
|
\begin{tabularx}{0.8\textwidth}{| c | Y | Y | Y | Y | Y |}
|
|
\thickhline
|
|
\multirow{2}{*}{\textbf{Output frequency}} &
|
|
\multicolumn{5}{c|}{\textbf{Phase noise (dBc/Hz) at carrier offset}}\\
|
|
\cline{2-6} & 1 kHz & 10 kHz & 100 kHz & 1 MHz & 10 MHz \\
|
|
\hline
|
|
125 MHz & -114 & -116 & -115 & -132 & -133 \\
|
|
\hline
|
|
500 MHz & -107 & -129 & -111 & -130 & -132 \\
|
|
\hline
|
|
1 GHz & -102 & -106 & -107 & -125 & -133 \\
|
|
\hline
|
|
2 GHz & -102 & -98 & -104 & -123 & -124 \\
|
|
\hline
|
|
3.5 GHz & -96 & -101 & -103 & -127 & -128 \\
|
|
\thickhline
|
|
\end{tabularx}
|
|
\end{threeparttable}
|
|
\end{table}
|
|
|
|
\newpage
|
|
|
|
\begin{figure}[H]
|
|
\centering
|
|
\includegraphics[height=3in]{mirny_phase_noise_frequency.png}
|
|
\caption{Phase noise measurement}
|
|
\end{figure}
|
|
|
|
\codesection{4456 Synthesizer Mirny}
|
|
|
|
\subsection{1 GHz sinusoidal wave}
|
|
Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
|
|
|
|
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
|
|
|
|
\subsection{ADF5356 power control}
|
|
Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
|
|
|
|
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
|
|
|
|
The parameter corresponds to a specific change of output power according to the following table\repeatfootnote{adf5356}.
|
|
|
|
\begin{center}
|
|
\captionof{table}{Power changes from ADF5356}
|
|
\begin{tabular}{|c|c|}
|
|
\hline
|
|
Parameter & Power \\ \hline
|
|
0 & -4 dBm \\ \hline
|
|
1 & -1 dBm \\ \hline
|
|
2 & +2 dBm \\ \hline
|
|
3 & +5 dBm \\ \hline
|
|
\end{tabular}
|
|
\end{center}
|
|
|
|
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
|
|
|
|
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
|
|
|
|
\subsection{Periodic 100\textmu s pulses}
|
|
The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
|
|
|
|
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
|
|
|
|
\ordersection{4456 Synthesizer Mirny}
|
|
|
|
\finalfootnote
|
|
|
|
\end{document}
|