forked from sinara-hw/datasheets
135 lines
4.1 KiB
Python
135 lines
4.1 KiB
Python
from artiq.experiment import *
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from artiq.coredevice.ad9910 import *
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class Sinusoid(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.cpld = self.get_device("urukul0_cpld")
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self.dds0 = self.get_device("urukul0_ch0")
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@kernel
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def run(self):
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self.core.reset()
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self.cpld.init()
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self.dds0.init()
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self.dds0.cfg_sw(True)
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self.dds0.set_att(6.*dB)
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self.dds0.set(10*MHz)
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class SynchronizedSinusoid(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.cpld = self.get_device("urukul0_cpld")
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self.dds0 = self.get_device("urukul0_ch0")
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self.dds1 = self.get_device("urukul0_ch1")
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@kernel
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def run(self):
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self.core.reset()
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self.cpld.init()
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self.dds0.init()
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self.dds0.cfg_sw(True)
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self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds0.set_att(6.*dB)
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self.dds1.init()
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self.dds1.cfg_sw(True)
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self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds1.set_att(6.*dB)
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self.dds0.set(frequency=10*MHz, phase=0.0)
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self.dds1.set(frequency=10*MHz, phase=0.25) # 0.25 turns phase offset
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class PulseRAM(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.cpld = self.get_device("urukul0_cpld")
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self.dds0 = self.get_device("urukul0_ch0")
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self.dds1 = self.get_device("urukul0_ch1")
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def prepare(self):
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self.amp = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order
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self.asf_ram = [0] * len(self.amp)
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@kernel
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def init_dds(self, dds):
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self.core.break_realtime()
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dds.init()
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dds.set_att(6.*dB)
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dds.cfg_sw(True)
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@kernel
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def configure_ram_mode(self, dds):
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self.core.break_realtime()
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dds.set_cfr1(ram_enable=0)
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self.cpld.io_update.pulse_mu(8)
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self.cpld.set_profile(0) # Enable the corresponding RAM profile
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# Profile 0 is the default
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dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
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step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
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self.cpld.io_update.pulse_mu(8)
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dds.amplitude_to_ram(self.amp, self.asf_ram)
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dds.write_ram(self.asf_ram)
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self.core.break_realtime()
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dds.set(frequency=5*MHz, ram_destination=RAM_DEST_ASF)
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# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
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dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
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self.cpld.io_update.pulse_mu(8)
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.cpld.init()
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self.init_dds(self.dds0)
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self.configure_ram_mode(self.dds0)
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class AmpRAM(PulseRAM):
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def prepare(self):
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# Reversed Order
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self.amp = [1.0, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, 0.0]
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self.asf_ram = [0] * len(self.amp)
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class SynchronizedPulseRAM(PulseRAM):
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@kernel
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def configure_ram_mode(self, dds):
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self.core.break_realtime()
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dds.set_cfr1(ram_enable=0)
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self.cpld.io_update.pulse_mu(8)
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self.cpld.set_profile(0) # Enable the corresponding RAM profile
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# Profile 0 is the default
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dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
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step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
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self.cpld.io_update.pulse_mu(8)
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dds.amplitude_to_ram(self.amp, self.asf_ram)
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dds.write_ram(self.asf_ram)
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self.core.break_realtime()
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dds.set(frequency=5*MHz, phase=0.0, ram_destination=RAM_DEST_ASF)
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# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
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dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
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self.cpld.io_update.pulse_mu(8)
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.cpld.init()
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self.init_dds(self.dds0)
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self.init_dds(self.dds1)
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self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
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self.configure_ram_mode(self.dds0)
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self.configure_ram_mode(self.dds1)
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