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\documentclass [10pt] { datasheet}
\usepackage { palatino}
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\usepackage [justification=centering] { caption}
\usepackage [utf8] { inputenc}
\usepackage [english] { babel}
\usepackage [english] { isodate}
\usepackage { graphicx}
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\usepackage { subfig}
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\usepackage { tikz}
\usepackage { pgfplots}
\usepackage { circuitikz}
\usetikzlibrary { calc}
\usetikzlibrary { fit,backgrounds}
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\title { 5432 DAC Zotino}
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\author { M-Labs Limited}
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\date { January 2022}
\revision { Revision 2}
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\companylogo { \includegraphics [height=0.73in] { artiq_ sinara.pdf} }
\begin { document}
\maketitle
\section { Features}
\begin { itemize}
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\item { 32-channel DAC.}
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\item { 16-bits resolution.}
\item { 1 MSPS shared between all channels.}
\item { Output voltage $ \pm $ 10V.}
\item { HD68 connector.}
\item { Can be broken out to BNC/SMA/MCX.}
\end { itemize}
\section { Applications}
\begin { itemize}
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\item { Controlling setpoints of PID controllers for laser power stabilization.}
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\item { Low-frequency arbitrary waveform generation.}
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\item { Driving DC electrodes in ion traps.}
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\end { itemize}
\section { General Description}
The 5432 Zotino is a 4hp EEM module part of the ARTIQ Sinara family.
It adds digital-analog converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
It provides 4 groups of 8 analog channels each, exposed by 1 HD68 connector.
Each channel supports output voltage from -10 V to 10 V.
All channels can be updated simultaneously.
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Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
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% Switch to next column
\vfill \break
\newcommand * { \MyLabel } [3][2cm]{ \parbox { #1} { \centering #2 \\ #3} }
\newcommand * { \MymyLabel } [3][4cm]{ \parbox { #1} { \centering #2 \\ #3} }
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\newcommand { \repeatfootnote } [1]{ \textsuperscript { \ref { #1} } }
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\newcommand { \inputcolorboxminted } [2]{ %
\begin { tcolorbox} [colback=white]
\inputminted [#1, gobble=4] { python} { #2}
\end { tcolorbox}
}
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\begin { figure} [h]
\centering
\scalebox { 0.88} {
\begin { circuitikz} [european, scale=0.95, every label/.append style={ align=center} ]
% HD68 Connector
\draw (0, 0) node[muxdemux, muxdemux def={ Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0} , circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) { HD68} ;
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% IDC Connectors to IDC cards
\draw (2.2, 1.2) node[twoportshape, t={ \MyLabel { IDC} { DAC 16-23} } , circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) { } ;
\draw (1.4, 1.2) node[twoportshape, t={ \MyLabel { IDC} { DAC 24-31} } , circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) { } ;
\draw (2.2, -1.2) node[twoportshape, t={ \MyLabel { IDC} { DAC 8-15} } , circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) { } ;
\draw (1.4, -1.2) node[twoportshape, t={ \MyLabel { IDC} { DAC 0-7} } , circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) { } ;
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% Op-amp x32
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\draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) { } ;
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% DAC AD5372
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\draw (4.6, 0.2) node[twoportshape, t=\MyLabel { 32-CH} { DAC} , circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (dac) { } ;
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% LVDS Transceivers
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\draw (6.6, 0) node[twoportshape, t=\MymyLabel { LVDS} { Transceiever} , circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) { } ;
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\draw (6.6, -1.6) node[twoportshape, t=\MymyLabel { LVDS} { Transceiever} , circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) { } ;
% Aesthetic EEPROM
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\draw (6.6, 1.6) node[twoportshape, t={ EEPROM} , circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eeprom) { } ;
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% EEMs from core device / controllers
\draw (8.2, 0.0) node[twoportshape, t={ EEM Port} , circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem_ in) { } ;
% Connect EEM IN to LVDS & EEMPROM
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\draw [latexslim-latexslim] (eeprom.north) -- (7.85, 1.6);
\draw [latexslim-latexslim] (lvds0.north) -- (7.85, 0);
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\draw [latexslim-latexslim] (lvds1.north) -- (7.85, -1.6);
% Connect LVDS to DAC
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\draw [latexslim-latexslim] (lvds0.south) -- (5.2, 0);
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\draw [latexslim-latexslim] (lvds1.south) -- (4.6, -1.6) -- (dac.south);
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% Connect DAC to Op-amp, label op-amp width x32
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\draw [-latexslim] (4, 0) -- (amp.west);
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\node [label=below:\tiny { Op-amp x32} ] at (3.2, -0.2) { } ;
\node [label=below:\tiny { 1 per ch.} ] at (3.2, -0.45) { } ;
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% Connect Op-amp to EEM OUT and HD68
\draw [-latexslim] (amp.east) -- (hd68.east);
\draw [-latexslim] (2.2, 0) -- (eem2.east);
\draw [-latexslim] (1.4, 0) -- (eem3.east);
\draw [-latexslim] (2.2, 0) -- (eem1.west);
\draw [-latexslim] (1.4, 0) -- (eem0.west);
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% TEC Cooler on top of the DAC
% To make it more obvious that it is cooling the DAC
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\draw (4.6, 1.45) node[twoportshape, t=\MymyLabel { TEC} { Cooler} , circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (tec_ cooler) { } ;
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% TEC Controller lined up with EEM IN
\draw (8.2, 3.5) node[twoportshape, t=\MymyLabel { TEC Controller} { Connector} , circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (tec_ conn) { } ;
% Thermistor for TEC controller
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\draw (6.6, 3.3) node[thermistorshape, scale=0.7, rotate=-90] (thermistor) { } ;
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\draw [latexslim-] (7.85, 3.3) -- (6.75, 3.3);
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% Connect the controller to the cooler
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\draw [-latexslim] (7.85, 4.2) -- (4.6, 4.2) -- (tec_ cooler.north);
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% Thermal connection between DAC and thermistor
\draw [densely dotted] (thermistor.south) -- (5.6, 3.3) -- (5.6, 0.5) -- (5.2, 0.5);
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\end { circuitikz}
}
\caption { Simplified Block Diagram}
\end { figure}
\begin { figure} [h]
\centering
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\includegraphics [height=2in] { Zotino_ FP.jpg}
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\includegraphics [height=2in] { photo5432.jpg}
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\caption { Zotino Card photo}
\end { figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\section { Electrical Specifications}
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% \hypersetup{hidelinks}
% \urlstyle{same}
The specifications are based on the datasheet of the DAC IC
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(AD5372BCPZ\footnote { \label { dac} https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_ 5373.pdf} ),
and various information from Sinara wiki\footnote { \label { zotino_ wiki} https://github.com/sinara-hw/Zotino/wiki} .
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\begin { table} [h]
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\centering
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\begin { threeparttable}
\caption { Output Specifications}
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\begin { tabularx} { 0.8\textwidth } { l | c c c | c | X}
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\thickhline
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\textbf { Parameter} & \textbf { Min.} & \textbf { Typ.} & \textbf { Max.} &
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\textbf { Unit} & \textbf { Conditions} \\
\hline
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Output voltage & -10 & & 10 & V & \\
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\hline
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Output impedance\repeatfootnote { zotino_ wiki} & \multicolumn { 4} { c|} { 470 $ \Omega $ $ || $ 2.2nF} & \\
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\hline
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Resolution\repeatfootnote { dac} & & 16 & & bits & \\
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\hline
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3dB bandwidth\repeatfootnote { zotino_ wiki} & & 75 & & kHz & \\
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\hline
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Power consumption\repeatfootnote { zotino_ wiki} & 3 & & 8.7 & W & \\
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\thickhline
\end { tabularx}
\end { threeparttable}
\end { table}
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The following are cross-talk and transient behavior of Zotino\footnote { \label { zotino21} https://github.com/sinara-hw/Zotino/issues/21} .
In terms of output noise, it was measured after 15 cm IDC cable, IDC-SMA, 100 cm coax ($ \sim $ 50 pF), and 500 k$ \Omega $ $ || $ 150 pF\footnote { \label { zotino27} https://github.com/sinara-hw/Zotino/issues/27} .
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The DAC output during noise measurement is 3.5 V.
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\begin { table} [h]
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\centering
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\begin { threeparttable}
\caption { Electrical Characteristics}
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\begin { tabularx} { 0.8\textwidth } { l | c c c | c | X}
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\thickhline
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\textbf { Parameter} & \textbf { Min.} & \textbf { Typ.} & \textbf { Max.} &
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\textbf { Unit} & \textbf { Conditions / Comments} \\
\hline
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DC cross-talk\repeatfootnote { zotino21} & & -116 & & dB & \\
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\hline
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Fall-time\repeatfootnote { zotino21} & & 18.5 & & $ \mu $ s & 10\% to 90\% fall-time \\
& & 25 & & $ \mu $ s & 1\% to 99\% fall-time \\
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\hline
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Negative overshoot\repeatfootnote { zotino21} & & 0.5\% & & - & \\
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\hline
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Rise-time\repeatfootnote { zotino21} & & 30 & & $ \mu $ s & 1\% to 99\% rise-time \\
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\hline
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Positive overshoot\repeatfootnote { zotino21} & & 0.65\% & & - & \\
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\hline
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Output noise\repeatfootnote { zotino27} & & & & & \\
\hspace { 18mm} @ 100 Hz & & 500 & & nV/rtHz & 6.9 Hz bandwidth \\
\hspace { 18mm} @ 300 Hz & & 300 & & nV/rtHz & 6.9 Hz bandwidth \\
\hspace { 18mm} @ 50 kHz & & 210 & & nV/rtHz & 6.9 kHz bandwidth \\
\hspace { 18mm} @ 1 MHz & & 4.6 & & nV/rtHz & 6.9 kHz bandwidth \\
\hspace { 18mm} $ > $ 4 MHz & & & 1 & nV/rtHz & 6.9 kHz bandwidth \\
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\thickhline
\end { tabularx}
\end { threeparttable}
\end { table}
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\newpage
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Step response are found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observe the waveform\repeatfootnote { zotino21} .
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\begin { figure} [hbt!]
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\centering
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\subfloat [\centering Switching from -10V to +10V] { {
\includegraphics [height=1.8in] { zotino_ step_ response_ rising.png}
} } %
\subfloat [\centering Switching from +10V to -10V] { {
\includegraphics [height=1.8in] { zotino_ step_ response_ falling.png}
} } %
\caption { Step response} %
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\end { figure}
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Far-end crosstalk is measured using the following setup\repeatfootnote { zotino21} .
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\begin { enumerate}
\item CH1 as aggressor, CH0 as victim
\item CH0, 2-7 terminated, CH 8-31 open
\item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables \& connectors.
\end { enumerate}
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\begin { figure} [hbt!]
\centering
\includegraphics [width=3.3in] { zotino_ fext.png}
\caption { Step crosstalk}
\end { figure}
\newpage
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\section { Front Panel Drawings}
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\begin { multicols} { 2}
\begin { center}
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\centering
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\includegraphics [height=3in] { zotino_ drawings.pdf}
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\captionof { figure} { 5432 DAC Zotino front panel drawings}
\end { center}
\begin { center}
\captionof { table} { Bill of Material (Standalone)}
\tiny
\begin { tabular} { |c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90503572 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end { tabular}
\end { center}
\columnbreak
\begin { center}
\centering
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\includegraphics [height=3in] { zotino_ assembly.pdf}
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\captionof { figure} { 5432 DAC Zotino front panel assembly}
\end { center}
\begin { center}
\captionof { table} { Bill of Material (Assembled)}
\tiny
\begin { tabular} { |c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90503572 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
6 & 3040012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
7 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
\end { tabular}
\end { center}
\end { multicols}
\newpage
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\section { Example ARTIQ code}
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The sections below demonstrate simple usage scenarios of the 5432 DAC Zotino card with the ARTIQ control system.
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They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url { https://m-labs.hk} .
\subsection { Set output voltage}
The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channel 0, 1, 2, 3 respectively.
Voltages of all 4 channels are updated simultaneously with the use of \texttt { set\char `_ dac()} .
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\inputcolorboxminted { firstline=11,lastline=22} { examples/zotino.py}
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\newpage
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\subsection { Triangular Wave}
A triangular waveform at 10 Hz, 16 V peak-to-peak.
Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
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Import \texttt { scipy.signal} and \texttt { numpy} modules to run this example.
\inputcolorboxminted { firstline=30,lastline=49} { examples/zotino.py}
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\section { Ordering Information}
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To order, please visit \url { https://m-labs.hk} and select the 5432 DAC Zotino in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url { mailto:sales@m-labs.hk} .
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\section * { }
\vspace * { \fill }
\begin { footnotesize}
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Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
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\end { footnotesize}
\end { document}
