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\section{Electrical Specifications}
External clock parameters are derived based on the internal termination specified in UG471\footnote{\label{ug471}https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO},
and the voltage range specified in DS181\footnote{\label{ds181}https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}.
The figure had accounted for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}).
\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
% 100R termination & 100/350/600 mV differential input after the transformer.
&\multicolumn{4}{c|}{10/100/125 MHz}& RTIO clock synthesized from input \\
\cline{2-6}
\hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm &\\
\hline
Power supply rating &\multicolumn{4}{c|}{12V, 5A}&\\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
\section{Distributed RTIO (DRTIO)}
DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central core device.
Multiple core devices (e.g. Kasli 2.0) can be interconnected through DRTIO. All core devices in the DRTIO system are classified as 1 of the 2 roles:
\begin{enumerate}
\item DRTIO Master \\
The DRTIO master is unique in a DRTIO system. It controls the DRTIO satellites(s) and local RTIO channels.
\item DRTIO Satellite \\
The rest of the core devices are DRTIO satellites. DRTIO satellites need an upstream connection to one other core devices (master or satellite).
It may provide downstream conenction to other DRTIO satellties.
\end{enumerate}
\section{Network Interface}
Communication between the host and the core device(s) is implemented using small form-factor pluggable (SFP) interfaces.
Approprate SFP transceivers must be plugged inside the corresponding SFP cages to enable communication between core devices.
\subsection{Upstream Connection}
A core device (e.g. Kasli 2.0) must acquire an upstream network connection through the \texttt{SFP0} slot.
\begin{itemize}
\item Standalone/DRTIO master \\
An Ethernet capable SFP transceiver must be inserted to the \texttt{SFP0} slot.
Typically, a RJ45 SFP module is inserted to the slot with an Ethernet cable with network connection attached to the module.
\item DRTIO Satellite \\
The \texttt{SFP0} port of DRTIO satellite should be connected to an appropriate SFP slot of the upstream core device (DRTIO master or satellite) with cable connection with SFP transceivers.
\end{itemize}
\subsection{Downstream Connection}
The 1124 Carrier Kasli 2.0 supports up to 3 DRTIO satellite connections per device.
DRTIO satellites can be connected using any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) through cable connections with SFP transceivers.
\section{Clock Routing}
\subsection{DRTIO Master/Standalone}
The RTIO clock is typically synthesized by the Si5324 clock multiplier, and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors.
An external reference can be supplied to synthesize the clock, which is supplied to the SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis.
Kasli 2.0 supports a set of clock systhesizing options for the (D)RTIO system:
\begin{table}[H]
\centering
\begin{tabular}{|c|c|c|}
\hline
RTIO frequency & Configuration & Clock generation \\\hline
Alternatively, the clock synthesizer can be bypassed using the \texttt{ext0\char`_bypass} clocking option, where the RTIO clock is directly supplied to the SMA connector.
The resulting clock signal is then routed to both the RTIO system and downstream DRTIO satellites.
Clocking options should be configured by setting the value of the \texttt{rtio} key to the desired configuration through \texttt{artiq\char`_coremgmt}.
For example, the RTIO frequency is synthesized from the external 10 MHz from the SMA connector after issuing the following command.
