759 lines
23 KiB
Python
759 lines
23 KiB
Python
from migen import *
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from migen.genlib.misc import WaitTimer
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from migen.genlib.fifo import SyncFIFO
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from util import PriorityEncoderMSB
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class SingleLineTX(Module):
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def __init__(self):
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self.txdata = Signal(5)
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self.ser_out = Signal()
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self.t_out = Signal()
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# TX SERDES
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self.specials += Instance("OSERDESE2",
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p_DATA_RATE_OQ="SDR", p_DATA_RATE_TQ="BUF",
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p_DATA_WIDTH=5, p_TRISTATE_WIDTH=1,
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p_INIT_OQ=0b00000,
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o_OQ=self.ser_out, o_TQ=self.t_out,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys5x"),
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i_CLKDIV=ClockSignal(),
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i_D1=self.txdata[0],
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i_D2=self.txdata[1],
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i_D3=self.txdata[2],
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i_D4=self.txdata[3],
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i_D5=self.txdata[4],
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i_TCE=1, i_OCE=1,
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# TODO: Hardcode t_in? Output disable is always unnecessary?
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i_T1=0)
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class SingleLineRX(Module):
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def __init__(self):
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self.rxdata = Signal(10)
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self.ser_in_no_dly = Signal()
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self.ld = Signal()
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self.ce = Signal()
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self.cnt_in = Signal(5)
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self.cnt_out = Signal(5)
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self.master_bitslip = Signal()
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self.slave_bitslip = Signal()
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ser_in = Signal()
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shifts = Signal(2)
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self.specials += [
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# Master deserializer
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Instance("ISERDESE2",
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p_DATA_RATE="DDR",
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p_DATA_WIDTH=10,
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p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1,
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p_SERDES_MODE="MASTER",
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p_IOBDELAY="IFD",
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o_Q1=self.rxdata[9],
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o_Q2=self.rxdata[8],
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o_Q3=self.rxdata[7],
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o_Q4=self.rxdata[6],
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o_Q5=self.rxdata[5],
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o_Q6=self.rxdata[4],
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o_Q7=self.rxdata[3],
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o_Q8=self.rxdata[2],
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o_SHIFTOUT1=shifts[0],
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o_SHIFTOUT2=shifts[1],
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i_DDLY=ser_in,
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i_BITSLIP=self.master_bitslip,
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i_CLK=ClockSignal("rx_sys5x"),
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i_CLKB=~ClockSignal("rx_sys5x"),
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i_CE1=1,
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i_RST=ResetSignal("rx_sys"),
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i_CLKDIV=ClockSignal("rx_sys")),
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# Slave deserializer
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Instance("ISERDESE2",
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p_DATA_RATE="DDR",
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p_DATA_WIDTH=10,
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p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1,
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p_SERDES_MODE="SLAVE",
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p_IOBDELAY="IFD",
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o_Q3=self.rxdata[1],
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o_Q4=self.rxdata[0],
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# i_DDLY=ser_in,
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i_BITSLIP=self.slave_bitslip,
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i_CLK=ClockSignal("rx_sys5x"),
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i_CLKB=~ClockSignal("rx_sys5x"),
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i_CE1=1,
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i_RST=ResetSignal("rx_sys"),
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i_CLKDIV=ClockSignal("rx_sys"),
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i_SHIFTIN1=shifts[0],
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i_SHIFTIN2=shifts[1]),
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# Tunable delay
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Instance("IDELAYE2",
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p_DELAY_SRC="IDATAIN",
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p_SIGNAL_PATTERN="DATA",
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p_CINVCTRL_SEL="FALSE",
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p_HIGH_PERFORMANCE_MODE="TRUE",
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# REFCLK refers to the clock source of IDELAYCTRL
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p_REFCLK_FREQUENCY=200.0,
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p_PIPE_SEL="FALSE",
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p_IDELAY_TYPE="VAR_LOAD",
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p_IDELAY_VALUE=0,
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i_C=ClockSignal("rx_sys"),
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i_LD=self.ld,
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i_CE=self.ce,
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i_LDPIPEEN=0,
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i_INC=1, # Always increment
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# Set the optimal delay tap via the aligner
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i_CNTVALUEIN=self.cnt_in,
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# Allow the aligner to check the tap value
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o_CNTVALUEOUT=self.cnt_out,
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i_IDATAIN=self.ser_in_no_dly,
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o_DATAOUT=ser_in
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),
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# IDELAYCTRL is with the clocking
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]
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class BitSlipReader(Module):
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def __init__(self):
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# IN
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self.loopback_rxdata = Signal(10)
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self.start = Signal()
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# Wait for stabilization after bitslip
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self.submodules.stab_timer = WaitTimer(511)
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# OUT
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self.done = Signal()
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self.bitslip = Signal()
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self.data_result = Array(Signal(10) for _ in range(5))
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self.slip_count = Signal(3)
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fsm = FSM(reset_state="WAIT_START")
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self.submodules += fsm
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fsm.act("WAIT_START",
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If(self.start,
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NextState("WAIT_TIMER"),
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).Else(
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NextState("WAIT_START"),
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)
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)
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fsm.act("WAIT_TIMER",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE"),
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)
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)
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fsm.act("SAMPLE",
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# Wait is reset now
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# Explicit assignment is unnecessary, as combinatorial statement
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# falls back to he default value when not driven
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# Keep result alive until reset
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NextValue(self.data_result[self.slip_count], self.loopback_rxdata),
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NextValue(self.slip_count, self.slip_count + 1),
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NextState("HIGH_BITSLIP_FIRST"),
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)
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# Pulsing BITSLIP alternate between 1 right shift and 3 left shifts
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# We are trying to figure out which 2-bits are the slave copying from
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# Hence, we only want shifts by 2. Pulsing twice does exactly that.
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fsm.act("HIGH_BITSLIP_FIRST",
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self.bitslip.eq(1),
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NextState("LOW_BITSLIP"),
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)
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fsm.act("LOW_BITSLIP",
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# bitslip signal is auto-reset
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NextState("HIGH_BITSLIP_SECOND"),
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)
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fsm.act("HIGH_BITSLIP_SECOND",
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self.bitslip.eq(1),
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If(self.slip_count == 5,
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NextState("TERMINATE"),
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).Else(
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NextState("WAIT_TIMER"),
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)
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)
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fsm.act("TERMINATE",
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self.done.eq(1),
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NextState("TERMINATE"),
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)
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class SlaveAligner(Module):
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def __init__(self):
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# IN
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self.loopback_rxdata = Signal(10)
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self.start = Signal()
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# Wait for stabilization after bitslip
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self.submodules.stab_timer = WaitTimer(511)
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# OUT
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self.done = Signal()
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self.master_bitslip = Signal()
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self.slave_bitslip = Signal()
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slip_count = Signal(3)
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check_odd = Signal()
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check_even = Signal()
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fsm = FSM(reset_state="WAIT_START")
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self.submodules += fsm
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fsm.act("WAIT_START",
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If(self.start,
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NextState("WAIT_TIMER"),
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)
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)
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fsm.act("WAIT_TIMER",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE"),
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)
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)
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fsm.act("SAMPLE",
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# Wait is reset now
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# Explicit assignment is unnecessary, as combinatorial statement
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# falls back to he default value when not driven
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# Detect the last 2 bits
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# If signal is received, detune the master bitslip if necessary
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If(self.loopback_rxdata[0] | self.loopback_rxdata[1],
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NextValue(check_odd, self.loopback_rxdata[1]),
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NextValue(check_even, self.loopback_rxdata[0]),
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NextState("CHECK_MASTER_BITSLIP"),
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).Else(
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NextValue(slip_count, slip_count + 1),
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NextState("HIGH_BITSLIP_FIRST"),
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)
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)
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# Pulsing BITSLIP alternate between 1 right shift and 3 left shifts
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# We are trying to figure out which 2-bits are the slave copying from
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# Hence, we only want shifts by 2. Pulsing twice does exactly that.
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fsm.act("HIGH_BITSLIP_FIRST",
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self.master_bitslip.eq(1),
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self.slave_bitslip.eq(1),
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NextState("LOW_BITSLIP"),
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)
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fsm.act("LOW_BITSLIP",
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# bitslip signal is auto-reset
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NextState("HIGH_BITSLIP_SECOND"),
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)
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fsm.act("HIGH_BITSLIP_SECOND",
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self.master_bitslip.eq(1),
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self.slave_bitslip.eq(1),
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If(slip_count == 5,
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NextState("SHIFT_WAIT_TIMER"),
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).Else(
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NextState("WAIT_TIMER"),
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)
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)
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odd_master_rxdata = self.loopback_rxdata[3::2]
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even_master_rxdata = self.loopback_rxdata[2::2]
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# Alternatively, we align the master with the slave
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fsm.act("CHECK_MASTER_BITSLIP",
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# At any point if the odd and/or even bits from the master reads 0
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# It implies the detuning is completed
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NextState("SHIFT_WAIT_TIMER"),
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If(check_odd & (odd_master_rxdata != 0),
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NextState("MASTER_HIGH_BITSLIP_FIRST"),
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),
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If(check_even & (even_master_rxdata != 0),
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NextState("MASTER_HIGH_BITSLIP_FIRST"),
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),
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)
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fsm.act("MASTER_HIGH_BITSLIP_FIRST",
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self.master_bitslip.eq(1),
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NextState("MASTER_LOW_BITSLIP"),
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)
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fsm.act("MASTER_LOW_BITSLIP",
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# bitslip signal is auto-reset
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NextState("MASTER_HIGH_BITSLIP_SECOND"),
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)
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fsm.act("MASTER_HIGH_BITSLIP_SECOND",
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self.master_bitslip.eq(1),
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NextState("MASTER_WAIT_TIMER"),
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)
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fsm.act("MASTER_WAIT_TIMER",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("CHECK_MASTER_BITSLIP"),
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)
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)
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# After eliminating the potentially duplicating pattern,
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# Shift the entire output pattern for delay tap optimization
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# Ideally, the optimized first edge would be the middle pair
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# So, shift it until bit 3/4 is set but bit 5 is not set
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fsm.act("SHIFT_WAIT_TIMER",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SHIFT_SAMPLE_PATTERN"),
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)
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)
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fsm.act("SHIFT_SAMPLE_PATTERN",
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If((self.loopback_rxdata[3:5] != 0) & ~self.loopback_rxdata[5],
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NextState("TERMINATE"),
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).Else(
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NextState("SHIFT_HIGH_BITSLIP_FIRST"),
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)
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)
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fsm.act("SHIFT_HIGH_BITSLIP_FIRST",
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self.master_bitslip.eq(1),
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self.slave_bitslip.eq(1),
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NextState("SHIFT_LOW_BITSLIP"),
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)
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fsm.act("SHIFT_LOW_BITSLIP",
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# bitslip signal is auto-reset
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NextState("SHIFT_HIGH_BITSLIP_SECOND"),
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)
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fsm.act("SHIFT_HIGH_BITSLIP_SECOND",
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self.master_bitslip.eq(1),
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self.slave_bitslip.eq(1),
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NextState("SHIFT_WAIT_TIMER")
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)
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fsm.act("TERMINATE",
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self.done.eq(1),
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NextState("TERMINATE"),
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)
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class PhaseReader(Module):
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def __init__(self):
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# Drive IDELAYE2 CE pin to increment delay
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# The signal should only last for 1 cycle
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self.inc_en = Signal()
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self.loopback_rxdata = Signal(10)
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self.delay_tap = Signal(5)
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# Pull up to start the phase reader
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self.start = Signal()
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self.data_result = Array(Signal(10) for _ in range(32))
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self.done = Signal()
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# Wait for stabilization after increment
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self.submodules.stab_timer = WaitTimer(511)
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fsm = FSM(reset_state="WAIT_START")
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self.submodules += fsm
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fsm.act("WAIT_START",
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If(self.start,
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NextState("WAIT_TIMER"),
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).Else(
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NextState("WAIT_START"),
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)
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)
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fsm.act("WAIT_TIMER",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE"),
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)
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)
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fsm.act("SAMPLE",
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# Wait is reset now
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# Explicit assignment is unnecessary, as combinatorial statement
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# falls back to he default value when not driven
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# Keep result alive until reset
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NextValue(self.data_result[self.delay_tap], self.loopback_rxdata),
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NextState("HIGH_CE"),
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)
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fsm.act("HIGH_CE",
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self.inc_en.eq(1),
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NextState("LOW_CE"),
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)
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fsm.act("LOW_CE",
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# TAP OUT is available 1 cycle after the pulse
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# Explicit signal reset is unnecessary, as signal assigned by
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# combinatorial logic in FSM is after leaving the setting block
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NextState("READ_TAP"),
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)
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fsm.act("READ_TAP",
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If(self.delay_tap != 0,
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NextState("WAIT_TIMER"),
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).Else(
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NextState("PROBE_FIN"),
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)
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)
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fsm.act("PROBE_FIN",
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self.done.eq(1),
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NextState("PROBE_FIN"),
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)
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class DelayOptimizer(Module):
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def __init__(self):
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# IN
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# Signals from the channel
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self.loopback_rxdata = Signal(10)
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self.delay_tap = Signal(5)
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# IN
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# Signal to start the calculation
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self.start = Signal()
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# OUT
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# Signal for controlling the channel delay tap
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self.ld = Signal()
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self.inc_en = Signal()
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# OUT
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# The optimal delay
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self.opt_delay_tap = Signal(5)
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# OUT
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# Keep even/odd indices, decimate the other
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self.select_odd = Signal()
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# OUT
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# Optimal delay is calculated
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self.done = Signal()
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# Priority encoder for finding the pulse location
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self.submodules.pulse_encoder = PriorityEncoderMSB(10)
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# Wait for stabilization after increment
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self.submodules.stab_timer = WaitTimer(511)
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# Intermediate signals
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self.expected_pulse = Signal(max=9)
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self.min_delay = Signal(5)
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self.max_offset = Signal(5)
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# Translate rxdata into array to allow indexing
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self.rxdata_array = Array(Signal() for _ in range(10))
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self.comb += [ self.rxdata_array[i].eq(self.loopback_rxdata[i]) for i in range(10) ]
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fsm = FSM(reset_state="WAIT_START")
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self.submodules += fsm
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fsm.act("WAIT_START",
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If(self.start,
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NextState("WAIT_ZERO"),
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).Else(
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NextState("WAIT_START"),
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)
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)
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fsm.act("WAIT_ZERO",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE_ZERO"),
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)
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)
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fsm.act("SAMPLE_ZERO",
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# Oversampling should guarantee the detection
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# However, priority encoder itself does not wraparound
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# So, we need to avoid passing wrapped around pulse signal into
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# the priority encoder.
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If(self.loopback_rxdata[0] & self.loopback_rxdata[-1],
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NextValue(self.expected_pulse, 1),
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).Else(
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self.pulse_encoder.i.eq(self.loopback_rxdata),
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If(self.pulse_encoder.o == 9,
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NextValue(self.expected_pulse, 0),
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).Else(
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NextValue(self.expected_pulse, self.pulse_encoder.o + 1),
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)
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),
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# Goto the next delay tap and wait for the pulse.
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NextState("INC_PULSE_DELAY_IN"),
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)
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fsm.act("WAIT_PULSE_IN",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE_PULSE_IN"),
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)
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)
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fsm.act("SAMPLE_PULSE_IN",
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If(self.rxdata_array[self.expected_pulse],
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NextValue(self.min_delay, self.delay_tap),
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NextState("INC_PULSE_DELAY_OUT"),
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).Else(
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NextState("INC_PULSE_DELAY_IN"),
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)
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)
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fsm.act("INC_PULSE_DELAY_IN",
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# This signal is automatically deasserted after this state
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self.inc_en.eq(1),
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NextState("WAIT_PULSE_IN"),
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)
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fsm.act("WAIT_PULSE_OUT",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE_PULSE_OUT"),
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)
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)
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fsm.act("SAMPLE_PULSE_OUT",
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If(~self.rxdata_array[self.expected_pulse],
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NextValue(self.opt_delay_tap, self.min_delay + (self.max_offset >> 1)),
|
|
NextState("LOAD_OPT_DELAY"),
|
|
).Else(
|
|
NextValue(self.max_offset, self.max_offset + 1),
|
|
NextState("INC_PULSE_DELAY_OUT"),
|
|
)
|
|
)
|
|
|
|
fsm.act("INC_PULSE_DELAY_OUT",
|
|
# This signal is automatically deasserted after this state
|
|
self.inc_en.eq(1),
|
|
NextState("WAIT_PULSE_OUT"),
|
|
)
|
|
|
|
fsm.act("LOAD_OPT_DELAY",
|
|
self.ld.eq(1),
|
|
# The optimal delay tap is prepared in the SAMPLE_PULSE_OUT state
|
|
NextState("WAIT_DELAY_LOAD"),
|
|
)
|
|
|
|
fsm.act("WAIT_DELAY_LOAD",
|
|
If(self.delay_tap == self.opt_delay_tap,
|
|
NextState("TERMINATE"),
|
|
),
|
|
)
|
|
|
|
fsm.act("TERMINATE",
|
|
self.done.eq(1),
|
|
self.select_odd.eq(self.expected_pulse[0]),
|
|
NextState("TERMINATE"),
|
|
)
|
|
|
|
|
|
class SyncSingleRX(Module):
|
|
def __init__(self):
|
|
# Ports
|
|
# IN: Undelayed serial signal
|
|
self.ser_in_no_dly = Signal()
|
|
# OUT: Received data after self-alignment, decimation
|
|
self.rxdata = Signal(5)
|
|
# OUT: RXDATA from this channel is self-aligned
|
|
self.align_done = Signal()
|
|
|
|
# Components
|
|
self.submodules.rx = SingleLineRX()
|
|
self.submodules.slave_aligner = SlaveAligner()
|
|
self.submodules.delay_solver = DelayOptimizer()
|
|
|
|
# Sample decimation
|
|
select_odd = Signal()
|
|
decimated_rxdata = Signal(5)
|
|
|
|
# Dataflow
|
|
self.comb += [
|
|
# Delay and oversample the original signal
|
|
self.rx.ser_in_no_dly.eq(self.ser_in_no_dly),
|
|
|
|
# Use the deserialized signals for alignment
|
|
self.slave_aligner.loopback_rxdata.eq(self.rx.rxdata),
|
|
self.delay_solver.loopback_rxdata.eq(self.rx.rxdata),
|
|
|
|
# Decimate the oversampled signals
|
|
If(select_odd,
|
|
decimated_rxdata.eq(self.rx.rxdata[1::2]),
|
|
).Else(
|
|
decimated_rxdata.eq(self.rx.rxdata[::2]),
|
|
),
|
|
|
|
# Send it to the output
|
|
self.rxdata.eq(decimated_rxdata),
|
|
]
|
|
|
|
# Control signals
|
|
self.comb += [
|
|
# Bitslip alignment
|
|
self.rx.master_bitslip.eq(self.slave_aligner.master_bitslip),
|
|
self.rx.slave_bitslip.eq(self.slave_aligner.slave_bitslip),
|
|
|
|
# Tap delay optimization
|
|
self.rx.ce.eq(self.delay_solver.inc_en),
|
|
self.rx.ld.eq(self.delay_solver.ld),
|
|
self.rx.cnt_in.eq(self.delay_solver.opt_delay_tap),
|
|
self.delay_solver.delay_tap.eq(self.rx.cnt_out),
|
|
]
|
|
|
|
self.submodules.fsm = FSM(reset_state="WAIT_SIGNAL")
|
|
|
|
self.fsm.act("WAIT_SIGNAL",
|
|
If(self.rx.rxdata != 0,
|
|
NextState("WAIT_ALIGNER")
|
|
),
|
|
)
|
|
|
|
self.fsm.act("WAIT_ALIGNER",
|
|
self.slave_aligner.start.eq(1),
|
|
If(self.slave_aligner.done,
|
|
NextState("WAIT_DELAY_OPT"),
|
|
),
|
|
)
|
|
|
|
self.fsm.act("WAIT_DELAY_OPT",
|
|
self.delay_solver.start.eq(1),
|
|
If(self.delay_solver.done,
|
|
NextValue(select_odd, self.delay_solver.select_odd),
|
|
NextState("INTRA_ALIGN_DONE"),
|
|
),
|
|
)
|
|
|
|
self.fsm.act("INTRA_ALIGN_DONE",
|
|
self.align_done.eq(1),
|
|
NextState("INTRA_ALIGN_DONE"),
|
|
)
|
|
|
|
|
|
class MultiLineTX(Module):
|
|
def __init__(self):
|
|
# Ports
|
|
# IN: Unserialized data
|
|
self.txdata = Signal(20)
|
|
# OUT: Serialized data
|
|
self.ser_out = Signal(4)
|
|
# OUT: 3-state signal output
|
|
self.t_out = Signal(4)
|
|
|
|
for idx in range(4):
|
|
single_tx = SingleLineTX()
|
|
|
|
self.comb += [
|
|
self.ser_out[idx].eq(single_tx.ser_out),
|
|
self.t_out[idx].eq(single_tx.t_out),
|
|
single_tx.txdata.eq(self.txdata[5*idx:5*(idx+1)]),
|
|
]
|
|
|
|
self.submodules += single_tx
|
|
|
|
|
|
class MultiLineRX(Module):
|
|
def __init__(self):
|
|
# Ports
|
|
# IN: Undelayed serial signal
|
|
self.ser_in_no_dly = Signal(4)
|
|
# OUT: Received data after self-alignment, decimation
|
|
self.rxdata = Signal(20)
|
|
# OUT: RXDATA from all channels are self-aligned
|
|
self.align_done = Signal()
|
|
# OUT: Group delay compensated
|
|
self.delay_done = Signal()
|
|
# OUT: Group delay adjustment failed
|
|
self.err = Signal()
|
|
|
|
channel_align_done = Signal(4)
|
|
self.comb += self.align_done.eq(channel_align_done == 0b1111)
|
|
|
|
buffer_outflow = Signal(4)
|
|
self.comb += buffer_outflow.eq(0b1111)
|
|
|
|
for idx in range(4):
|
|
single_rx = SyncSingleRX()
|
|
|
|
self.comb += [
|
|
single_rx.ser_in_no_dly.eq(self.ser_in_no_dly[idx]),
|
|
# self.rxdata[5*idx:5*(idx+1)].eq(single_rx.rxdata),
|
|
channel_align_done[idx].eq(single_rx.align_done),
|
|
]
|
|
|
|
# FIFOs for handling group delay
|
|
# Signal from each OSERDES group can have a different delay
|
|
# So, add delay to the groups that receives the pulse early
|
|
# Maximum delay = 8
|
|
channel_buffer = SyncFIFO(5, 16)
|
|
|
|
self.comb += [
|
|
# Allow data go through the FIFO unless aligning
|
|
# Pay the memory delay cost
|
|
channel_buffer.we.eq(1),
|
|
channel_buffer.re.eq(buffer_outflow[idx]),
|
|
|
|
# Data always flow from individual RX to the rxdata port
|
|
channel_buffer.din.eq(single_rx.rxdata),
|
|
self.rxdata[5*idx:5*(idx+1)].eq(channel_buffer.dout),
|
|
]
|
|
|
|
# If at any point the FIFO fills up,
|
|
# group delay can no longer be determined and compensated
|
|
self.sync += [
|
|
If(~channel_buffer.writable,
|
|
self.err.eq(1),
|
|
),
|
|
]
|
|
|
|
self.submodules += [ single_rx, channel_buffer ]
|
|
|
|
self.submodules.fsm = FSM(reset_state="WAIT_ALIGN_DONE")
|
|
|
|
self.fsm.act("WAIT_ALIGN_DONE",
|
|
If(self.align_done,
|
|
NextState("WAIT_ZERO"),
|
|
),
|
|
)
|
|
|
|
self.fsm.act("WAIT_ZERO",
|
|
If(self.rxdata == 0,
|
|
NextState("WAIT_PULSE"),
|
|
),
|
|
)
|
|
|
|
self.fsm.act("WAIT_PULSE",
|
|
# Control outflow until all channels finds the pulse
|
|
If(self.rxdata == 0b11111111111111111111,
|
|
buffer_outflow.eq(0b1111),
|
|
self.delay_done.eq(1),
|
|
NextState("GROUP_DELAY_DONE"),
|
|
).Else(
|
|
buffer_outflow[0].eq(self.rxdata[ 0: 5] == 0),
|
|
buffer_outflow[1].eq(self.rxdata[ 5:10] == 0),
|
|
buffer_outflow[2].eq(self.rxdata[10:15] == 0),
|
|
buffer_outflow[3].eq(self.rxdata[15:20] == 0),
|
|
),
|
|
)
|
|
|
|
self.fsm.act("GROUP_DELAY_DONE",
|
|
self.delay_done.eq(1),
|
|
NextState("GROUP_DELAY_DONE"),
|
|
)
|