333 lines
9.8 KiB
Python
333 lines
9.8 KiB
Python
from migen import *
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from sync_serdes import PhaseReader, DelayOptimizer, BitSlipReader, SlaveAligner
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import random
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def reader_testbench(dut, rxdata_list):
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yield dut.delay_tap.eq(0)
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yield dut.start.eq(1)
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assert (yield dut.stab_timer.wait) == 0
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for i in range(32):
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yield dut.loopback_rxdata.eq(rxdata_list[i])
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yield
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yield
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assert (yield dut.stab_timer.wait) == 1
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# Keep yielding until the DUT gives CE signal
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while (yield dut.inc_en) == 0:
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yield
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# Check that inc_en is deassrted after 1 clock cycle
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yield
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assert (yield dut.inc_en) == 0
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# Load a new tap value
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yield dut.delay_tap.eq(i + 1)
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yield
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# Nothing to check in the READ_TAP state
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yield
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assert(yield dut.done) == 1
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for i in range(32):
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signal = yield dut.data_result[i]
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expected = rxdata_list[i]
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assert signal == expected
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for i in range(200):
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assert (yield dut.inc_en) == 0
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yield
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# Untouched delay: Record should be invariant
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for i in range(32):
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signal = yield dut.data_result[i]
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expected = rxdata_list[i]
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assert signal == expected
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def optimal_delay_testbench(dut, pulse_list, cycles, pulse_index, min_delay, max_offset, opt_delay_tap):
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# Start the module
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yield dut.delay_tap.eq(0)
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yield dut.start.eq(1)
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assert (yield dut.stab_timer.wait) == 0
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for i in range(cycles):
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# Pass in a new rxdata for sampling
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# The stab_timer should start waiting after
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yield dut.loopback_rxdata.eq(pulse_list[i])
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yield
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yield
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assert (yield dut.stab_timer.wait) == 1
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# Eventually, the wait will end
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# Either it triggers an increment or a finished signal
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# And we will get the expected pulse location
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# inc_en is pulsed after this is found
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if i == (cycles - 1):
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while (yield dut.done) == 0:
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yield
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break
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else:
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while (yield dut.inc_en) == 0:
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yield
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# Then we increment the rxdata index
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yield dut.delay_tap.eq(i + 1)
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yield
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# Fast-forward to the result
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# while (yield dut.done) == 0:
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# yield
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assert (yield dut.done) == 1
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assert (yield dut.expected_pulse) == pulse_index
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assert (yield dut.min_delay) == min_delay
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assert (yield dut.max_offset) == max_offset
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assert (yield dut.opt_delay_tap) == opt_delay_tap
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for _ in range(100):
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yield
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# Invariant test: Everything is frozen after done
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assert (yield dut.done) == 1
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assert (yield dut.expected_pulse) == pulse_index
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assert (yield dut.min_delay) == min_delay
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assert (yield dut.max_offset) == max_offset
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assert (yield dut.opt_delay_tap) == opt_delay_tap
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def bitslip_reader_tb(dut, rxdata_list):
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# Start the module
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yield dut.start.eq(1)
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assert (yield dut.stab_timer.wait) == 0
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for i in range(5):
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yield dut.loopback_rxdata.eq(rxdata_list[i])
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yield
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yield
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assert (yield dut.stab_timer.wait) == 1
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# Keep yielding until the DUT gives BITSLIP signal
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while (yield dut.bitslip) == 0:
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yield
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# There will be 2 BITSLIP pulses
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# Both BITSLIP pulses should last for 1 cycle
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assert (yield dut.bitslip) == 1
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yield
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assert (yield dut.bitslip) == 0
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yield
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assert (yield dut.bitslip) == 1
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yield
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assert (yield dut.bitslip) == 0
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assert (yield dut.done) == 1
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# The result in the module should contain all rxdata
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for i, rxdata in enumerate(rxdata_list):
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assert (yield dut.data_result[i]) == rxdata
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yield
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yield
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def bitslip_aligner_tb(dut, rxdata_list, adjust_list):
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# Start the module
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yield dut.start.eq(1)
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assert (yield dut.stab_timer.wait) == 0
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for i in range(len(rxdata_list)):
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yield dut.loopback_rxdata.eq(rxdata_list[i])
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yield
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yield
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assert (yield dut.stab_timer.wait) == 1
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# Wait until the timer runs out
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while (yield dut.stab_timer.done) == 0:
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yield
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# There will not be unnecessary pulses
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if i == (len(rxdata_list) - 1):
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break
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# Keep yielding until the DUT gives BITSLIP signal
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while (((yield dut.master_bitslip) == 0) and ((yield dut.slave_bitslip) == 0)):
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yield
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# There will be 2 BITSLIP pulses
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# Both BITSLIP pulses should last for 1 cycle
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assert (yield dut.master_bitslip) == 1
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assert (yield dut.slave_bitslip) == 1
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yield
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assert (yield dut.master_bitslip) == 0
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assert (yield dut.slave_bitslip) == 0
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yield
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assert (yield dut.master_bitslip) == 1
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assert (yield dut.slave_bitslip) == 1
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yield
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assert (yield dut.master_bitslip) == 0
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assert (yield dut.slave_bitslip) == 0
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# Skip ahead 2 cycles for state transitions
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yield
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yield
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for i in range(len(adjust_list)):
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# Eventually the master bitslip signal will be pulled up
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while (yield dut.master_bitslip) == 0:
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yield
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assert (yield dut.master_bitslip) == 1
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assert (yield dut.slave_bitslip) == 0
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yield
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assert (yield dut.master_bitslip) == 0
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assert (yield dut.slave_bitslip) == 0
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yield
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assert (yield dut.master_bitslip) == 1
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assert (yield dut.slave_bitslip) == 0
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yield
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assert (yield dut.master_bitslip) == 0
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assert (yield dut.slave_bitslip) == 0
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# Give the new rxdata
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yield dut.loopback_rxdata.eq(adjust_list[i])
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while (yield dut.stab_timer.done) == 0:
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yield
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yield
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yield
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assert (yield dut.done) == 1
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# # Random testing for delay reader
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# for _ in range(32):
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# rxdata_list = [ random.getrandbits(10) for _ in range(32) ]
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# dut = PhaseReader()
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# run_simulation(dut, reader_testbench(dut, rxdata_list), vcd_name="phase_reader.vcd")
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# # Random testing for optimal delay calculation
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# # Generate a delay list
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# start = random.randint(0, 9)
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# start_length = random.randint(1, 10)
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# offset = random.randint(4, 5)
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# current_index = start
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# remaining_length = start_length
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# single_pulse_list = []
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# expected_index = (current_index + 1) % 10
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# expected_length = 10
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# for tap in range(32 + offset):
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# single_pulse_list.append(1 << current_index)
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# remaining_length -= 1
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# if remaining_length == 0:
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# current_index = (current_index + 1) % 10
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# remaining_length = 10
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# pulse_list = list(single_pulse_list)
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# for i in range(offset, 32):
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# pulse_list[i] |= single_pulse_list[i - offset]
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# found_start_edge = False
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# max_offset = 0
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# # Calculate min_delay
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# for i, pulse in enumerate(pulse_list):
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# if (pulse & (1 << expected_index)) != 0:
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# if not found_start_edge:
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# min_delay = i
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# found_start_edge = True
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# else:
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# max_offset += 1
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# if (pulse & (1 << expected_index)) == 0 and found_start_edge:
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# cycles = i + 1
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# break
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# print(min_delay)
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# print(max_offset)
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# print(cycles)
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# opt_delay = int(min_delay + (max_offset / 2))
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# print(opt_delay)
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# # Simulate
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# dut = DelayOptimizer()
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# run_simulation(dut, optimal_delay_testbench(
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# dut, pulse_list, cycles, expected_index,
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# min_delay, max_offset, opt_delay),
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# vcd_name="delay_opt.vcd"
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# )
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# # Random test for bitslip reader
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# for _ in range(32):
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# rxdata_list = [ random.getrandbits(10) for _ in range(5) ]
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# dut = BitSlipReader()
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# run_simulation(dut, bitslip_reader_tb(dut, rxdata_list), vcd_name="bitslip_reader.vcd")
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# Test for bitslip alignment
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def generate_aligner_tb_list(mocked_pair, start_pair):
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print("Mocked pair", str(mocked_pair))
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print("Start pair", str(start_pair))
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double_bit_pattern = bool(random.randint(0, 1))
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pulsed_indices = [ random.randint(0, 9) ]
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print("Pulsed indices", str(pulsed_indices))
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if double_bit_pattern:
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pulsed_indices.append((pulsed_indices[0] + 1) % 10)
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def generate_rxdata(pair_shift):
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mocked_data = 0
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rxdata = 0
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for index in pulsed_indices:
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rxdata |= (1 << ((index + 2*pair_shift) % 10))
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mocking_mask = (1 << (2*mocked_pair)) | (1 << ((2*mocked_pair) + 1))
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mocked_data = ((rxdata & mocking_mask) >> (2*mocked_pair))
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# Wipe out the 2 lsb
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rxdata &= 0x3FC
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# Copy the mocked data to the 2 lsb
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rxdata |= mocked_data
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return mocked_data, rxdata
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rxdata_list = []
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for i in range(5):
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mocked_data, rxdata = generate_rxdata((start_pair + i) % 5)
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rxdata_list.append(rxdata)
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if mocked_data:
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break
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print("Mocked data", str(mocked_data))
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def is_mocking(original):
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if original == 0:
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return False
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if (original & 0b11) == mocked_data:
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return True
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return is_mocking(original >> 2)
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adjust_list = []
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master_rxdata = rxdata_list[-1] & 0x3FC
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if mocked_data and is_mocking(master_rxdata):
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# Keep adding shifted variant to the adjust_list
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# Until the 2 lsb is not mocking other pairs
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while True:
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master_rxdata <<= 2
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master_rxdata &= 0x3FF
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adjust_list.append(master_rxdata | mocked_data)
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if not is_mocking(master_rxdata):
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break
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return rxdata_list, adjust_list
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for mocked_pair in range(5):
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for start_pair in range(5):
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for _ in range(12):
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rxdata_list, adjust_list = generate_aligner_tb_list(mocked_pair, start_pair)
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print(rxdata_list)
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print(adjust_list)
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dut = SlaveAligner()
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run_simulation(dut, bitslip_aligner_tb(dut, rxdata_list, adjust_list), vcd_name="bitslip_aligner.vcd")
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print(mocked_pair, start_pair)
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