221 lines
7.2 KiB
Python
221 lines
7.2 KiB
Python
from migen import *
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from sync_serdes import *
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from migen.genlib.fifo import SyncFIFO
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from migen.build.platforms.sinara import kasli
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from migen.genlib.misc import WaitTimer
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from kasli_crg import KasliCRG
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from eem_helpers import generate_pads
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from uart import UART
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from io_loopback import SingleIOLoopback
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SEPARATOR = Constant(0b0101)
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class SingleSerDesLoopBack(Module):
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def __init__(self, io_pad, sys_clk_freq):
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self.uart_rx = Signal()
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self.uart_tx = Signal()
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self.submodules.uart = UART(round((115200/sys_clk_freq)*2**32))
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self.comb += [
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self.uart.phy_rx.eq(self.uart_rx),
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self.uart_tx.eq(self.uart.phy_tx),
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]
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self.submodules.tx = SingleLineTX()
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self.submodules.rx = SingleLineRX()
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self.submodules.bitslip_reader = BitSlipReader()
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self.submodules.slave_aligner = SlaveAligner()
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self.submodules.post_align_reader = BitSlipReader()
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# self.submodules.delay_optimizer = DelayOptimizer()
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# The actual channel
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self.submodules.channel = SingleIOLoopback(io_pad)
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# Attach FIFO to UART TX, send rate is too slow w.r.t sysclk
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self.submodules.tx_fifo = SyncFIFO(8, 64)
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self.comb += [
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# Repetitively send 0b00100
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self.tx.txdata.eq(0b00100),
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# Loopback channel
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self.channel.i.eq(self.tx.ser_out),
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self.rx.ser_in_no_dly.eq(self.channel.o),
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self.channel.t.eq(self.tx.t_out),
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# TX path
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self.uart.tx_data.eq(self.tx_fifo.dout),
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self.uart.tx_stb.eq(self.tx_fifo.readable),
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self.tx_fifo.re.eq(self.uart.tx_ack),
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]
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# Route deserializer to phase_reader & the delay tap optimizer
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self.comb += [
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# Start the reader initially
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self.bitslip_reader.start.eq(1),
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# Delay tap optimizer will start after the reader is done
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# self.delay_optimizer.start.eq(0),
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self.slave_aligner.start.eq(0),
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self.post_align_reader.start.eq(0),
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# RXDATA for both reader and optimzer
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self.bitslip_reader.loopback_rxdata.eq(self.rx.rxdata),
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# TODO: Reconnet
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# self.delay_optimizer.loopback_rxdata.eq(self.rx.rxdata),
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self.slave_aligner.loopback_rxdata.eq(self.rx.rxdata),
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self.post_align_reader.loopback_rxdata.eq(self.rx.rxdata),
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# Delay tap value
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# self.phase_reader.delay_tap.eq(self.rx.cnt_out),
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# TODO: Reconnet
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# self.delay_optimizer.delay_tap.eq(self.rx.cnt_out),
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# Increment control enable, such that phase_reader can
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# increment tap value after delay measurement
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# Re-assign the incremnet control to the optimizer after the optimizer has started
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# If(self.delay_optimizer.start,
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# self.rx.ce.eq(self.delay_optimizer.inc_en),
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# ).Else(
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# self.rx.ce.eq(self.phase_reader.inc_en),
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# )
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# self.rx.ce.eq(self.phase_reader.inc_en),
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self.rx.master_bitslip.eq(
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self.bitslip_reader.bitslip |
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self.slave_aligner.master_bitslip |
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self.post_align_reader.bitslip
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),
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self.rx.slave_bitslip.eq(
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self.bitslip_reader.bitslip |
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self.slave_aligner.slave_bitslip |
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self.post_align_reader.bitslip
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),
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]
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# Show measured result on UART
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delay_tap = Signal(6)
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bitslip_count = Signal(3)
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post_align_bitslip_count = Signal(3)
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fsm = FSM(reset_state="WAIT_DONE")
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self.submodules += fsm
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fsm.act("WAIT_DONE",
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If(self.bitslip_reader.done,
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NextState("WRITE_UPPER"),
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),
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)
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fsm.act("WRITE_UPPER",
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# Exist state if all results are sent
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If(bitslip_count == 5,
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NextState("FIND_OPT_DELAY"),
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.bitslip_reader.data_result[bitslip_count][8:]),
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NextState("WRITE_LOWER"),
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),
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)
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fsm.act("WRITE_LOWER",
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.bitslip_reader.data_result[bitslip_count][:8]),
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NextValue(bitslip_count, bitslip_count + 1),
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NextState("WRITE_UPPER"),
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)
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fsm.act("FIND_OPT_DELAY",
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self.slave_aligner.start.eq(1),
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# self.rx.ce.eq(self.delay_optimizer.inc_en),
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If(self.slave_aligner.done,
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NextState("WRITE_DONE_UPPER"),
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).Else(
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NextState("FIND_OPT_DELAY")
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)
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)
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fsm.act("WRITE_DONE_UPPER",
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self.post_align_reader.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("WRITE_DONE_LOWER")
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)
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)
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fsm.act("WRITE_DONE_LOWER",
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self.post_align_reader.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("REREAD_BITSLIP")
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)
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)
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fsm.act("REREAD_BITSLIP",
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If(self.post_align_reader.done,
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NextState("REWRITE_UPPER"),
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).Else(
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NextState("REREAD_BITSLIP"),
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),
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)
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fsm.act("REWRITE_UPPER",
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# Exist state if all results are sent
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If(post_align_bitslip_count == 5,
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NextState("TERMINATE"),
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.post_align_reader.data_result[post_align_bitslip_count][8:]),
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NextState("REWRITE_LOWER"),
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),
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)
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fsm.act("REWRITE_LOWER",
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.post_align_reader.data_result[post_align_bitslip_count][:8]),
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NextValue(post_align_bitslip_count, post_align_bitslip_count + 1),
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NextState("REWRITE_UPPER"),
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)
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fsm.act("TERMINATE",
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NextState("TERMINATE"),
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)
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# # Output control
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# self.sync += [
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# # Send data to FIFO if not repeated
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# If(self.rxdata_r[:5] != self.rx.rxdata,
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# self.rxdata_r.eq(self.rx.rxdata),
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# self.tx_fifo.din.eq(self.rx.rxdata),
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# self.tx_fifo.we.eq(1)
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# ).Else(
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# self.tx_fifo.we.eq(0)
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# )
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# ]
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if __name__ == "__main__":
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platform = kasli.Platform(hw_rev="v2.0")
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# Generate pads for the I/O blocks
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eem = 3
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generate_pads(platform, eem)
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# pads = [
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# platform.request("dio{}".format(eem), i) for i in range(4)
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# ]
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pad = platform.request("dio{}".format(eem), 0)
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crg = KasliCRG(platform)
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top = SingleSerDesLoopBack(pad, crg.sys_clk_freq)
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# Wire up UART core to the pads
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uart_pads = platform.request("serial")
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top.comb += [
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top.uart_rx.eq(uart_pads.rx),
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uart_pads.tx.eq(top.uart_tx),
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]
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top.submodules += crg
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platform.build(top)
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