388 lines
12 KiB
Python
388 lines
12 KiB
Python
from migen import *
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from migen.genlib.misc import WaitTimer
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from util import PriorityEncoderMSB
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class SingleLineTX(Module):
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def __init__(self):
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self.txdata = Signal(5)
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self.ser_out = Signal()
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self.t_out = Signal()
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# TX SERDES
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self.specials += Instance("OSERDESE2",
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p_DATA_RATE_OQ="SDR", p_DATA_RATE_TQ="BUF",
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p_DATA_WIDTH=5, p_TRISTATE_WIDTH=1,
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p_INIT_OQ=0b00000,
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o_OQ=self.ser_out, o_TQ=self.t_out,
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys5x"),
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i_CLKDIV=ClockSignal(),
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i_D1=self.txdata[0],
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i_D2=self.txdata[1],
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i_D3=self.txdata[2],
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i_D4=self.txdata[3],
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i_D5=self.txdata[4],
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i_TCE=1, i_OCE=1,
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# TODO: Hardcode t_in? Output disable is always unnecessary?
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i_T1=0)
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class SingleLineRX(Module):
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def __init__(self):
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self.rxdata = Signal(10)
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self.ser_in_no_dly = Signal()
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self.ce = Signal()
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self.cnt_out = Signal(5)
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self.opt_delay = Signal(5)
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ser_in = Signal()
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shifts = Signal(2)
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self.specials += [
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# Master deserializer
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Instance("ISERDESE2",
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p_DATA_RATE="DDR",
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p_DATA_WIDTH=10,
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p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1,
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p_SERDES_MODE="MASTER",
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p_IOBDELAY="IFD",
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o_Q1=self.rxdata[9],
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o_Q2=self.rxdata[8],
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o_Q3=self.rxdata[7],
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o_Q4=self.rxdata[6],
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o_Q5=self.rxdata[5],
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o_Q6=self.rxdata[4],
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o_Q7=self.rxdata[3],
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o_Q8=self.rxdata[2],
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o_SHIFTOUT1=shifts[0],
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o_SHIFTOUT2=shifts[1],
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i_DDLY=ser_in,
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i_BITSLIP=0,
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i_CLK=ClockSignal("rx_sys5x"),
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i_CLKB=~ClockSignal("rx_sys5x"),
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i_CE1=1,
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i_RST=ResetSignal("rx_sys"),
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i_CLKDIV=ClockSignal("rx_sys")),
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# Slave deserializer
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Instance("ISERDESE2",
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p_DATA_RATE="DDR",
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p_DATA_WIDTH=10,
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p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1,
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p_SERDES_MODE="SLAVE",
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p_IOBDELAY="IFD",
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o_Q3=self.rxdata[1],
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o_Q4=self.rxdata[0],
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# i_DDLY=ser_in,
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i_BITSLIP=0,
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i_CLK=ClockSignal("rx_sys5x"),
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i_CLKB=~ClockSignal("rx_sys5x"),
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i_CE1=1,
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i_RST=ResetSignal("rx_sys"),
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i_CLKDIV=ClockSignal("rx_sys"),
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i_SHIFTIN1=shifts[0],
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i_SHIFTIN2=shifts[1]),
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# Tunable delay
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Instance("IDELAYE2",
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p_DELAY_SRC="IDATAIN",
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p_SIGNAL_PATTERN="DATA",
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p_CINVCTRL_SEL="FALSE",
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p_HIGH_PERFORMANCE_MODE="TRUE",
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# REFCLK refers to the clock source of IDELAYCTRL
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p_REFCLK_FREQUENCY=200.0,
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p_PIPE_SEL="FALSE",
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p_IDELAY_TYPE="VARIABLE",
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p_IDELAY_VALUE=0,
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i_C=ClockSignal("rx_sys"),
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# i_LD=self._dly_sel.storage[i//8] & self._rdly_dq_rst.re,
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# i_CE=self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
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i_LD=0,
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i_CE=self.ce, # TODO: Port output
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i_LDPIPEEN=0,
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i_INC=1, # Always increment
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# Allow aligner to check delay tap value
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o_CNTVALUEOUT=self.cnt_out,
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i_IDATAIN=self.ser_in_no_dly, o_DATAOUT=ser_in
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),
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# IDELAYCTRL is with the clocking
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]
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class BitSlipReader(Module):
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def __init__(self):
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# IN
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self.loopback_rxdata = Signal(10)
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self.start = Signal()
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# Wait for stabilization after bitslip
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self.submodules.stab_timer = WaitTimer(511)
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# OUT
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self.done = Signal()
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self.bitslip = Signal()
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self.data_result = Array(Signal(10) for _ in range(5))
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self.slip_count = Signal(3)
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fsm = FSM(reset_state="WAIT_START")
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self.submodules += fsm
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fsm.act("WAIT_START",
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If(self.start,
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NextState("WAIT_TIMER"),
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).Else(
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NextState("WAIT_START"),
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)
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)
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fsm.act("WAIT_TIMER",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE"),
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)
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)
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fsm.act("SAMPLE",
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# Wait is reset now
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# Explicit assignment is unnecessary, as combinatorial statement
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# falls back to he default value when not driven
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# Keep result alive until reset
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NextValue(self.data_result[self.slip_count], self.loopback_rxdata),
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NextValue(self.slip_count, self.slip_count + 1),
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NextState("HIGH_BITSLIP_FIRST"),
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)
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# Pulsing BITSLIP alternate between 1 right shift and 3 left shifts
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# We are trying to figure out which 2-bits are the slave copying from
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# Hence, we only want shifts by 2. Pulsing twice does exactly that.
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fsm.act("HIGH_BITSLIP_FIRST",
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self.bitslip.eq(1),
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NextState("LOW_BITSLIP"),
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)
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fsm.act("LOW_BITSLIP",
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# bitslip signal is auto-reset
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NextState("HIGH_BITSLIP_SECOND"),
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)
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fsm.act("HIGH_BITSLIP_SECOND",
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self.bitslip.eq(1),
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If(self.slip_count == 5,
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NextState("TERMINATE"),
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).Else(
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NextState("WAIT_TIMER"),
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)
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)
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fsm.act("TERMINATE",
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self.done.eq(1),
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NextState("TERMINATE"),
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)
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class PhaseReader(Module):
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def __init__(self):
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# Drive IDELAYE2 CE pin to increment delay
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# The signal should only last for 1 cycle
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self.inc_en = Signal()
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self.loopback_rxdata = Signal(10)
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self.delay_tap = Signal(5)
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# Pull up to start the phase reader
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self.start = Signal()
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self.data_result = Array(Signal(10) for _ in range(32))
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self.done = Signal()
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# Wait for stabilization after increment
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self.submodules.stab_timer = WaitTimer(511)
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fsm = FSM(reset_state="WAIT_START")
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self.submodules += fsm
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fsm.act("WAIT_START",
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If(self.start,
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NextState("WAIT_TIMER"),
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).Else(
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NextState("WAIT_START"),
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)
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)
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fsm.act("WAIT_TIMER",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE"),
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)
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)
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fsm.act("SAMPLE",
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# Wait is reset now
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# Explicit assignment is unnecessary, as combinatorial statement
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# falls back to he default value when not driven
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# Keep result alive until reset
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NextValue(self.data_result[self.delay_tap], self.loopback_rxdata),
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NextState("HIGH_CE"),
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)
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fsm.act("HIGH_CE",
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self.inc_en.eq(1),
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NextState("LOW_CE"),
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)
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fsm.act("LOW_CE",
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# TAP OUT is available 1 cycle after the pulse
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# Explicit signal reset is unnecessary, as signal assigned by
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# combinatorial logic in FSM is after leaving the setting block
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NextState("READ_TAP"),
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)
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fsm.act("READ_TAP",
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If(self.delay_tap != 0,
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NextState("WAIT_TIMER"),
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).Else(
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NextState("PROBE_FIN"),
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)
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)
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fsm.act("PROBE_FIN",
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self.done.eq(1),
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NextState("PROBE_FIN"),
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)
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class DelayOptimizer(Module):
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def __init__(self):
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# IN
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# Signals from the channel
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self.loopback_rxdata = Signal(10)
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self.delay_tap = Signal(5)
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# IN
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# Signal to start the calculation
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self.start = Signal()
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# OUT
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# Signal for controlling the channel delay tap
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self.inc_en = Signal()
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# OUT
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# The optimal delay
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self.opt_delay_tap = Signal(5)
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# OUT
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# Optimal delay is calculated
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self.done = Signal()
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# Priority encoder for finding the pulse location
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self.submodules.pulse_encoder = PriorityEncoderMSB(10)
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# Wait for stabilization after increment
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self.submodules.stab_timer = WaitTimer(511)
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# Intermediate signals
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self.expected_pulse = Signal(max=9)
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self.min_delay = Signal(5)
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self.max_offset = Signal(5)
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# Translate rxdata into array to allow indexing
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self.rxdata_array = Array(Signal() for _ in range(10))
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self.comb += [ self.rxdata_array[i].eq(self.loopback_rxdata[i]) for i in range(10) ]
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fsm = FSM(reset_state="WAIT_START")
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self.submodules += fsm
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fsm.act("WAIT_START",
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If(self.start,
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NextState("WAIT_ZERO"),
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).Else(
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NextState("WAIT_START"),
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)
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)
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fsm.act("WAIT_ZERO",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE_ZERO"),
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)
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)
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fsm.act("SAMPLE_ZERO",
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# Oversampling should guarantee the detection
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# However, priority encoder itself does not wraparound
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# So, we need to avoid passing wrapped around pulse signal into
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# the priority encoder.
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If(self.loopback_rxdata[0] & self.loopback_rxdata[-1],
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NextValue(self.expected_pulse, 1),
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).Else(
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self.pulse_encoder.i.eq(self.loopback_rxdata),
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If(self.pulse_encoder.o == 9,
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NextValue(self.expected_pulse, 0),
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).Else(
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NextValue(self.expected_pulse, self.pulse_encoder.o + 1),
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)
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),
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# Goto the next delay tap and wait for the pulse.
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NextState("INC_PULSE_DELAY_IN"),
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)
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fsm.act("WAIT_PULSE_IN",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE_PULSE_IN"),
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)
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)
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fsm.act("SAMPLE_PULSE_IN",
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If(self.rxdata_array[self.expected_pulse],
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NextValue(self.min_delay, self.delay_tap),
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NextState("INC_PULSE_DELAY_OUT"),
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).Else(
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NextState("INC_PULSE_DELAY_IN"),
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)
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)
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fsm.act("INC_PULSE_DELAY_IN",
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# This signal is automatically deasserted after this state
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self.inc_en.eq(1),
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NextState("WAIT_PULSE_IN"),
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)
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fsm.act("WAIT_PULSE_OUT",
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self.stab_timer.wait.eq(1),
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If(self.stab_timer.done,
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NextState("SAMPLE_PULSE_OUT"),
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)
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)
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fsm.act("SAMPLE_PULSE_OUT",
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If(~self.rxdata_array[self.expected_pulse],
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NextValue(self.opt_delay_tap, self.min_delay + (self.max_offset >> 1)),
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NextState("TERMINATE"),
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).Else(
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NextValue(self.max_offset, self.max_offset + 1),
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NextState("INC_PULSE_DELAY_OUT"),
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)
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)
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fsm.act("INC_PULSE_DELAY_OUT",
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# This signal is automatically deasserted after this state
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self.inc_en.eq(1),
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NextState("WAIT_PULSE_OUT"),
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)
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fsm.act("TERMINATE",
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self.done.eq(1),
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NextState("TERMINATE"),
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)
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