493 lines
16 KiB
Python
493 lines
16 KiB
Python
from migen import *
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from sync_serdes import *
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from migen.genlib.fifo import SyncFIFO
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from migen.build.platforms.sinara import kasli, efc
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from migen.genlib.misc import WaitTimer
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from kasli_crg import TransceiverCRG
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from eem_helpers import generate_pads
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from uart import UART
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from io_loopback import SingleIOLoopback
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SEPARATOR = Constant(0b0101)
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class SingleSerDesLoopBack(Module):
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def __init__(self, io_pad, sys_clk_freq, debug):
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self.uart_rx = Signal()
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self.uart_tx = Signal()
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self.submodules.uart = UART(round((115200/sys_clk_freq)*2**32))
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self.comb += [
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self.uart.phy_rx.eq(self.uart_rx),
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self.uart_tx.eq(self.uart.phy_tx),
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]
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self.submodules.tx = SingleLineTX()
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self.submodules.rx = SingleLineRX()
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# Primary adjustment to master-slave bitslip
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self.submodules.slave_aligner = SlaveAligner()
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# Optimal delay solver
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self.submodules.delay_solver = DelayOptimizer()
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# Debugging readers
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if debug:
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self.submodules.bitslip_reader = BitSlipReader()
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self.submodules.post_align_reader = BitSlipReader()
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self.submodules.phase_reader = PhaseReader()
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# The actual channel
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self.submodules.channel = SingleIOLoopback(io_pad)
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# Attach FIFO to UART TX, send rate is too slow w.r.t sysclk
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self.submodules.tx_fifo = SyncFIFO(8, 64)
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self.comb += [
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# Repetitively send 0b00100
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self.tx.txdata.eq(0b00100),
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# Loopback channel
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self.channel.i.eq(self.tx.ser_out),
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self.rx.ser_in_no_dly.eq(self.channel.o),
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self.channel.t.eq(self.tx.t_out),
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# TX path
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self.uart.tx_data.eq(self.tx_fifo.dout),
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self.uart.tx_stb.eq(self.tx_fifo.readable),
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self.tx_fifo.re.eq(self.uart.tx_ack),
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]
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# Route deserializer to phase_reader & the delay tap optimizer
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self.comb += [
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self.slave_aligner.start.eq(0),
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self.delay_solver.start.eq(0),
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# RXDATA for aligner & optimzer
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self.slave_aligner.loopback_rxdata.eq(self.rx.rxdata),
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self.delay_solver.loopback_rxdata.eq(self.rx.rxdata),
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# Delay tap value
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self.delay_solver.delay_tap.eq(self.rx.cnt_out),
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# IDELAY delay tap control, such that phase_reader can
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# change tap value after delay measurement
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self.rx.ce.eq(self.delay_solver.inc_en),
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self.rx.master_bitslip.eq(self.slave_aligner.master_bitslip),
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self.rx.slave_bitslip.eq(self.slave_aligner.slave_bitslip),
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self.rx.ld.eq(self.delay_solver.ld),
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self.rx.cnt_in.eq(self.delay_solver.opt_delay_tap),
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]
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# Debugging logics
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if debug:
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self.comb += [
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self.bitslip_reader.loopback_rxdata.eq(self.rx.rxdata),
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self.post_align_reader.loopback_rxdata.eq(self.rx.rxdata),
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self.phase_reader.loopback_rxdata.eq(self.rx.rxdata),
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self.phase_reader.delay_tap.eq(self.rx.cnt_out),
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self.rx.ce.eq(
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self.phase_reader.inc_en |
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self.delay_solver.inc_en
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),
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self.rx.master_bitslip.eq(
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self.bitslip_reader.bitslip |
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self.slave_aligner.master_bitslip |
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self.post_align_reader.bitslip
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),
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self.rx.slave_bitslip.eq(
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self.bitslip_reader.bitslip |
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self.slave_aligner.slave_bitslip |
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self.post_align_reader.bitslip
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),
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]
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if debug:
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delay_tap_count = Signal(6)
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bitslip_count = Signal(3)
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post_align_bitslip_count = Signal(3)
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rx_intra_aligned = Signal()
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select_odd = Signal()
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rxdata_decimated = Signal(5)
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rxdata_pulse_read = Signal(10)
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self.comb += [
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If(select_odd,
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rxdata_decimated.eq(self.rx.rxdata[1::2]),
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).Else(
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rxdata_decimated.eq(self.rx.rxdata[::2]),
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),
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]
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if not debug:
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release_fsm = FSM(reset_state="WAIT_ALIGNER")
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self.submodules += release_fsm
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release_fsm.act("WAIT_ALIGNER",
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self.slave_aligner.start.eq(1),
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If(self.slave_aligner.done,
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NextState("WAIT_DELAY_OPT"),
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),
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)
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release_fsm.act("WAIT_DELAY_OPT",
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self.delay_solver.start.eq(1),
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If(self.delay_solver.done,
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NextValue(select_odd, self.delay_solver.select_odd),
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NextState("INTRA_ALIGN_DONE"),
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),
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)
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release_fsm.act("INTRA_ALIGN_DONE",
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rx_intra_aligned.eq(1),
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NextState("WAIT_TX_ZERO"),
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)
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release_fsm.act("WAIT_TX_ZERO",
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If(rxdata_decimated == 0,
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NextState("WAIT_PULSE"),
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),
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)
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release_fsm.act("WAIT_PULSE",
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If(rxdata_decimated != 0,
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NextValue(rxdata_pulse_read, rxdata_decimated),
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NextState("NEXT_RXDATA"),
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),
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)
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next_rxdata = Signal(5)
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release_fsm.act("NEXT_RXDATA",
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NextValue(next_rxdata, rxdata_decimated),
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NextState("WRITE_PULSE_UPPER"),
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)
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release_fsm.act("WRITE_PULSE_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0),
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NextState("WRITE_PULSE_LOWER"),
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),
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)
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release_fsm.act("WRITE_PULSE_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(rxdata_pulse_read),
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NextState("WRITE_NEXT_UPPER"),
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),
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)
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release_fsm.act("WRITE_NEXT_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0),
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NextState("WRITE_NEXT_LOWER"),
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),
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)
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release_fsm.act("WRITE_NEXT_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(next_rxdata),
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NextState("TERMINATE"),
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),
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)
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release_fsm.act("TERMINATE",
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NextState("TERMINATE"),
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)
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else:
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fsm = FSM(reset_state="WAIT_DONE")
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self.submodules += fsm
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fsm.act("WAIT_DONE",
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self.bitslip_reader.start.eq(1),
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If(self.bitslip_reader.done,
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NextValue(bitslip_count, 0),
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NextState("WRITE_UPPER"),
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),
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)
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fsm.act("WRITE_UPPER",
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# Exist state if all results are sent
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If(bitslip_count == 5,
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NextState("START_SLAVE_ALIGNER"),
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.bitslip_reader.data_result[bitslip_count][8:]),
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NextState("WRITE_LOWER"),
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),
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)
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fsm.act("WRITE_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.bitslip_reader.data_result[bitslip_count][:8]),
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NextValue(bitslip_count, bitslip_count + 1),
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NextState("WRITE_UPPER"),
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)
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)
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fsm.act("START_SLAVE_ALIGNER",
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self.slave_aligner.start.eq(1),
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# self.rx.ce.eq(self.delay_optimizer.inc_en),
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If(self.slave_aligner.done,
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NextState("WRITE_DONE_UPPER"),
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).Else(
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NextState("START_SLAVE_ALIGNER")
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)
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)
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fsm.act("WRITE_DONE_UPPER",
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self.post_align_reader.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("WRITE_DONE_LOWER")
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)
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)
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fsm.act("WRITE_DONE_LOWER",
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self.post_align_reader.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("REREAD_BITSLIP")
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)
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)
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fsm.act("REREAD_BITSLIP",
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If(self.post_align_reader.done,
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NextState("REWRITE_UPPER"),
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).Else(
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NextState("REREAD_BITSLIP"),
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),
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)
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fsm.act("REWRITE_UPPER",
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# Exist state if all results are sent
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If(post_align_bitslip_count == 5,
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NextState("WRITE_B2P_DIVIDER_UPPER"),
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.post_align_reader.data_result[post_align_bitslip_count][8:]),
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NextState("REWRITE_LOWER"),
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),
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)
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fsm.act("REWRITE_LOWER",
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.post_align_reader.data_result[post_align_bitslip_count][:8]),
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NextValue(post_align_bitslip_count, post_align_bitslip_count + 1),
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NextState("REWRITE_UPPER"),
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)
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fsm.act("WRITE_B2P_DIVIDER_UPPER",
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self.phase_reader.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("WRITE_B2P_DIVIDER_LOWER"),
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)
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)
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fsm.act("WRITE_B2P_DIVIDER_LOWER",
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self.phase_reader.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("WAIT_PHASE_READER"),
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)
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)
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fsm.act("WAIT_PHASE_READER",
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If(self.phase_reader.done,
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NextState("WRITE_DELAY_UPPER"),
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).Else(
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NextState("WAIT_PHASE_READER"),
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)
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)
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fsm.act("WRITE_DELAY_UPPER",
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If(delay_tap_count == 32,
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NextState("DELAY_SOLVER_DIVIDER_UPPER")
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.phase_reader.data_result[delay_tap_count][8:]),
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NextState("WRITE_DELAY_LOWER"),
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),
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)
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fsm.act("WRITE_DELAY_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.phase_reader.data_result[delay_tap_count][:8]),
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NextValue(delay_tap_count, delay_tap_count + 1),
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NextState("WRITE_DELAY_UPPER")
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),
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)
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fsm.act("DELAY_SOLVER_DIVIDER_UPPER",
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self.delay_solver.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("DELAY_SOLVER_DIVIDER_LOWER"),
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)
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)
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fsm.act("DELAY_SOLVER_DIVIDER_LOWER",
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self.delay_solver.start.eq(1),
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0xFF),
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NextState("WAIT_DELAY_SOLVER"),
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)
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)
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fsm.act("WAIT_DELAY_SOLVER",
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If(self.delay_solver.done,
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NextValue(select_odd, self.delay_solver.select_odd),
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NextState("WRITE_UPPER_ZERO"),
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).Else(
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NextState("WAIT_DELAY_SOLVER"),
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)
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)
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fsm.act("WRITE_UPPER_ZERO",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0x00),
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NextState("WRITE_LOWER_OPT"),
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)
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)
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fsm.act("WRITE_LOWER_OPT",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.delay_solver.opt_delay_tap),
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NextState("WAIT_OPT_DELAY_ACTIVE"),
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),
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)
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fsm.act("WAIT_OPT_DELAY_ACTIVE",
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If(self.rx.cnt_out == self.delay_solver.opt_delay_tap,
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NextState("RESAMPLE_RXDATA_UPPER"),
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),
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)
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fsm.act("RESAMPLE_RXDATA_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.rx.rxdata[8:]),
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NextState("RESAMPLE_RXDATA_LOWER"),
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)
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)
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fsm.act("RESAMPLE_RXDATA_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.rx.rxdata[:8]),
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NextState("INTRA_ALIGN_DONE"),
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)
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)
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fsm.act("INTRA_ALIGN_DONE",
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rx_intra_aligned.eq(1),
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NextState("WAIT_TX_ZERO"),
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)
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fsm.act("WAIT_TX_ZERO",
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If(rxdata_decimated == 0,
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NextState("WAIT_PULSE"),
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),
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)
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fsm.act("WAIT_PULSE",
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If(rxdata_decimated != 0,
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NextValue(rxdata_pulse_read, rxdata_decimated),
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NextState("WRITE_PULSE_UPPER"),
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)
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)
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fsm.act("WRITE_PULSE_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(rxdata_pulse_read[8:]),
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NextState("WRITE_PULSE_LOWER"),
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)
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)
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fsm.act("WRITE_PULSE_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(rxdata_pulse_read[:8]),
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NextState("TERMINATE"),
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)
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)
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fsm.act("TERMINATE",
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NextState("TERMINATE"),
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)
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tx_fsm = FSM(reset_state="SEND_TRAINING")
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self.submodules += tx_fsm
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tx_fsm.act("SEND_TRAINING",
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self.tx.txdata.eq(0b00100),
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If(rx_intra_aligned,
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NextState("TX_ZERO"),
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),
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)
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# Intra-ISERDES alignment done, investigate group delay
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# TX is first set zero for around 16 cycles.
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tx_zero_counter = Signal(5)
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tx_fsm.act("TX_ZERO",
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self.tx.txdata.eq(0b00000),
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If(tx_zero_counter == 15,
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NextState("TX_HIGH"),
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).Else(
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NextValue(tx_zero_counter, tx_zero_counter + 1),
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),
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)
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tx_fsm.act("TX_HIGH",
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self.tx.txdata.eq(0b11111),
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NextState("TX_LOW"),
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)
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tx_fsm.act("TX_LOW",
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self.tx.txdata.eq(0b00000),
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)
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if __name__ == "__main__":
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# platform = kasli.Platform(hw_rev="v2.0")
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platform = efc.Platform()
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# Generate pads for the I/O blocks
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eem = 1
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generate_pads(platform, eem)
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pad = platform.request("dio{}".format(eem), 0)
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crg = TransceiverCRG(platform, platform.request("gtp_clk"))
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top = SingleSerDesLoopBack(pad, crg.sys_clk_freq, True)
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# Wire up UART core to the pads
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uart_pads = platform.request("serial")
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top.comb += [
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top.uart_rx.eq(uart_pads.rx),
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uart_pads.tx.eq(top.uart_tx),
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]
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top.submodules += crg
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platform.build(top)
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