106 lines
3.0 KiB
Python
106 lines
3.0 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg
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class UART(Module):
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def __init__(self, tuning_word):
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self.phy_rx = Signal()
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self.phy_tx = Signal()
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self.rx_data = Signal(8)
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self.rx_stb = Signal()
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self.tx_data = Signal(8)
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self.tx_stb = Signal()
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self.tx_ack = Signal()
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# # #
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#
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# RX
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#
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uart_clk_rxen = Signal()
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phase_accumulator_rx = Signal(32)
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rx = Signal()
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self.specials += MultiReg(self.phy_rx, rx)
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rx_r = Signal()
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rx_reg = Signal(8)
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rx_bitcount = Signal(4)
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rx_busy = Signal()
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rx_done = self.rx_stb
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rx_data = self.rx_data
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self.sync += [
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rx_done.eq(0),
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rx_r.eq(rx),
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If(~rx_busy,
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If(~rx & rx_r, # look for start bit
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rx_busy.eq(1),
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rx_bitcount.eq(0),
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)
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).Else(
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If(uart_clk_rxen,
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rx_bitcount.eq(rx_bitcount + 1),
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If(rx_bitcount == 0,
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If(rx, # verify start bit
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rx_busy.eq(0)
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)
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).Elif(rx_bitcount == 9,
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rx_busy.eq(0),
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If(rx, # verify stop bit
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rx_data.eq(rx_reg),
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rx_done.eq(1)
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)
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).Else(
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rx_reg.eq(Cat(rx_reg[1:], rx))
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)
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)
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)
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]
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self.sync += \
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If(rx_busy,
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + tuning_word)
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).Else(
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
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)
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#
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# TX
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#
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uart_clk_txen = Signal()
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phase_accumulator_tx = Signal(32)
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self.phy_tx.reset = 1
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tx_reg = Signal(8)
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tx_bitcount = Signal(4)
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tx_busy = Signal()
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self.sync += [
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self.tx_ack.eq(0),
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If(self.tx_stb & ~tx_busy & ~self.tx_ack,
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tx_reg.eq(self.tx_data),
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tx_bitcount.eq(0),
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tx_busy.eq(1),
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self.phy_tx.eq(0)
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).Elif(uart_clk_txen & tx_busy,
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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self.phy_tx.eq(1)
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).Elif(tx_bitcount == 9,
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self.phy_tx.eq(1),
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tx_busy.eq(0),
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self.tx_ack.eq(1),
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).Else(
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self.phy_tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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]
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self.sync += \
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If(tx_busy,
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Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word)
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).Else(
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Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
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)
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