231 lines
6.9 KiB
Python
231 lines
6.9 KiB
Python
from migen import *
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from sync_serdes import MultiLineRX, MultiLineTX
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from migen.genlib.fifo import SyncFIFO
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from migen.build.platforms.sinara import kasli, efc
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from kasli_crg import TransceiverCRG
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from eem_helpers import generate_pads
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from uart import UART
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from io_loopback import SingleIOLoopback, IOLoopBack
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class MultiSerDesLoopBack(Module):
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def __init__(self, io_pads, sys_clk_freq):
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self.uart_rx = Signal()
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self.uart_tx = Signal()
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self.submodules.uart = UART(round((115200/sys_clk_freq)*2**32))
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self.comb += [
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self.uart.phy_rx.eq(self.uart_rx),
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self.uart_tx.eq(self.uart.phy_tx),
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]
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self.submodules.tx = MultiLineTX()
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self.submodules.rx = MultiLineRX()
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# The actual channel
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self.submodules.channel = IOLoopBack(io_pads)
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# Attach FIFO to UART TX, send rate is too slow w.r.t sysclk
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self.submodules.tx_fifo = SyncFIFO(8, 64)
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self.comb += [
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# Repetitively send 0b00100
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# Note: Replicate() doesn't work, 0b00100 is lowered into 3'd4
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# I need 5'd4 for the replicate operator in Verilog
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self.tx.txdata.eq(0b00100001000010000100),
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# Loopback channel
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self.channel.i.eq(self.tx.ser_out),
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self.channel.t.eq(self.tx.t_out),
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self.rx.ser_in_no_dly.eq(self.channel.o),
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# TX path
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self.uart.tx_data.eq(self.tx_fifo.dout),
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self.uart.tx_stb.eq(self.tx_fifo.readable),
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self.tx_fifo.re.eq(self.uart.tx_ack),
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# Just start RX alignment, no reason to wait
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self.rx.start.eq(1),
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]
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self.submodules.rx_fsm = FSM(reset_state="WAIT_GROUP_ALIGN")
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sampled_rxdata = Array(Signal(20) for _ in range(16))
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sample_idx = Signal(4)
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self.rx_fsm.act("WAIT_GROUP_ALIGN",
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If(self.rx.err,
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NextState("WRITE_ERR_UPPER"),
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).Elif(self.rx.rxdata == 0b11111111111111111111,
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NextValue(sampled_rxdata[0], self.rx.rxdata),
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NextValue(sample_idx, 1),
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NextState("SAMPLE_RXDATA"),
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),
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)
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self.rx_fsm.act("WRITE_ERR_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0b01010101),
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NextState("WRITE_ERR_LOWER"),
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),
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)
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self.rx_fsm.act("WRITE_ERR_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(0b10101010),
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NextState("TERMINATE"),
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),
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)
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self.rx_fsm.act("SAMPLE_RXDATA",
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If(sample_idx == 15,
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NextValue(sample_idx, 0),
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NextState("WRITE_PATTERN_FIRST_UPPER"),
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).Else(
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NextValue(sampled_rxdata[sample_idx], self.rx.rxdata),
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NextValue(sample_idx, sample_idx + 1),
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),
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)
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self.rx_fsm.act("WRITE_PATTERN_FIRST_UPPER",
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If(sample_idx == 15,
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NextState("TERMINATE"),
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).Elif(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[sample_idx][8:10]),
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NextState("WRITE_PATTERN_FIRST_LOWER"),
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),
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)
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self.rx_fsm.act("WRITE_PATTERN_FIRST_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[sample_idx][:8]),
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NextState("WRITE_PATTERN_SECOND_UPPER"),
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),
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)
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self.rx_fsm.act("WRITE_PATTERN_SECOND_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[sample_idx][18:20]),
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NextState("WRITE_PATTERN_SECOND_LOWER"),
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),
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)
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self.rx_fsm.act("WRITE_PATTERN_SECOND_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(sampled_rxdata[sample_idx][10:18]),
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NextValue(sample_idx, sample_idx + 1),
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NextState("WRITE_PATTERN_FIRST_UPPER"),
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),
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)
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self.rx_fsm.act("TERMINATE",
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NextState("TERMINATE"),
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)
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self.submodules.tx_fsm = FSM(reset_state="SEND_TRAINING")
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self.tx_fsm.act("SEND_TRAINING",
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self.tx.txdata.eq(0b00100001000010000100),
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If(self.rx.align_done,
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NextState("SEND_ZERO"),
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),
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)
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send_zero_duration = Signal(2)
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self.tx_fsm.act("SEND_ZERO",
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self.tx.txdata.eq(0),
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If(send_zero_duration == 0b11,
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NextState("SEND_PULSE"),
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).Else(
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NextValue(send_zero_duration, send_zero_duration + 1),
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),
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)
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self.tx_fsm.act("SEND_PULSE",
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self.tx.txdata.eq(0b11111111111111111111),
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NextState("WAIT_GROUP_ALIGN"),
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)
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self.tx_fsm.act("WAIT_GROUP_ALIGN",
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self.tx.txdata.eq(0),
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If(self.rx.delay_done,
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NextState("SEND_ARB_DATA1"),
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),
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)
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self.tx_fsm.act("SEND_ARB_DATA1",
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self.tx.txdata.eq(0b00111001110011100111),
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NextState("SEND_ARB_DATA2"),
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)
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self.tx_fsm.act("SEND_ARB_DATA2",
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self.tx.txdata.eq(0),
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NextState("SEND_ARB_DATA3"),
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)
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self.tx_fsm.act("SEND_ARB_DATA3",
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self.tx.txdata.eq(0xDEADB),
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NextState("SEND_ARB_DATA4"),
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)
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self.tx_fsm.act("SEND_ARB_DATA4",
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self.tx.txdata.eq(0xBCAFE),
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NextState("TERMINATE"),
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)
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self.tx_fsm.act("TERMINATE",
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self.tx.txdata.eq(0),
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NextState("TERMINATE"),
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)
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if __name__ == "__main__":
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import argparse
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parser = argparse.ArgumentParser()
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parser.add_argument("platform")
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args = parser.parse_args()
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platform_dict = {
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"kasli": kasli.Platform(hw_rev="v2.0"),
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"efc": efc.Platform(),
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}
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sysclk_name = {
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"kasli": "clk125_gtp",
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"efc": "gtp_clk",
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}
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platform = platform_dict[args.platform]
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sysclk = platform.request(sysclk_name[args.platform])
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# Generate pads for the I/O blocks
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# Using EEM1 for both as both EFC and Kasli has EEM1
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# EEM1 are not interconnected
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eem = 1
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generate_pads(platform, eem)
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pads = [
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platform.request("dio{}".format(eem), i+4) for i in range(4)
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]
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# pad = platform.request("dio{}".format(eem), 0)
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crg = TransceiverCRG(platform, sysclk)
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top = MultiSerDesLoopBack(pads, crg.sys_clk_freq)
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# Wire up UART core to the pads
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uart_pads = platform.request("serial")
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top.comb += [
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top.uart_rx.eq(uart_pads.rx),
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uart_pads.tx.eq(top.uart_tx),
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]
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top.submodules += crg
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platform.build(top)
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