45 lines
1.3 KiB
Python
45 lines
1.3 KiB
Python
from migen import *
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from migen.build.platforms.sinara import kasli
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from migen.genlib.fifo import SyncFIFO
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from uart import UART
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from kasli_crg import KasliCRG
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class UARTLoopBack(Module):
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def __init__(self, sys_clk_freq):
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self.uart_rx = Signal()
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self.uart_tx = Signal()
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self.submodules.uart = UART(round((115200/sys_clk_freq)*2**32))
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self.comb += [
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self.uart.phy_rx.eq(self.uart_rx),
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self.uart_tx.eq(self.uart.phy_tx),
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]
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# Attach buffer between UART RX --> TX
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# This constitutes the loopback channel
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self.submodules.buffer = SyncFIFO(8, 64)
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self.comb += [
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self.buffer.din.eq(self.uart.rx_data),
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self.buffer.we.eq(self.uart.rx_stb),
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self.uart.tx_data.eq(self.buffer.dout),
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self.uart.tx_stb.eq(self.buffer.readable),
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self.buffer.re.eq(self.uart.tx_ack),
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]
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if __name__ == "__main__":
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platform = kasli.Platform(hw_rev="v2.0")
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crg = KasliCRG(platform)
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top = UARTLoopBack(crg.sys_clk_freq)
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# Wire up UART core to the pads
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uart_pads = platform.request("serial")
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top.comb += [
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top.uart_rx.eq(uart_pads.rx),
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uart_pads.tx.eq(top.uart_tx),
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]
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top.submodules += crg
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platform.build(top)
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