149 lines
5.2 KiB
Python
149 lines
5.2 KiB
Python
from migen import *
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from migen.build.platforms.sinara import kasli
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from migen.genlib.resetsync import AsyncResetSynchronizer
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class TransceiverCRG(Module):
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def __init__(self, platform, clk125, gte=True):
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self.platform = platform
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# Generated clock domains
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys5x = ClockDomain()
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self.clock_domains.cd_rx_sys = ClockDomain()
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self.clock_domains.cd_rx_sys5x = ClockDomain()
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self.clock_domains.cd_clk200 = ClockDomain()
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# Configure system clock using GTP ports
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self.sys_clk_freq = 125e6
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clk125_buf = Signal()
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clk125_div2 = Signal()
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if gte:
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=clk125.p, i_IB=clk125.n,
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o_O=clk125_buf,
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o_ODIV2=clk125_div2)
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else:
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self.specials += Instance("IBUFDS",
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i_I=clk125.p,
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i_IB=clk125.n,
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o_O=clk125_buf)
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div2_pll_fb = Signal()
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inner_pll_locked = Signal()
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self.specials += Instance("PLLE2_BASE",
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p_CLKIN1_PERIOD=8.0,
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i_CLKIN1=clk125_buf,
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i_CLKFBIN=div2_pll_fb,
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o_CLKFBOUT=div2_pll_fb,
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o_LOCKED=inner_pll_locked,
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# VCO @ 1GHz
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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# 200MHz for IDELAYCTRL
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p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=clk125_div2,
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),
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# MMCM to generate different frequencies
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mmcm_fb = Signal()
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mmcm_locked = Signal()
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mmcm_sys = Signal()
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mmcm_sys5x = Signal()
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mmcm_rx_sys = Signal()
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mmcm_rx_sys5x = Signal()
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# PLL to IDELAYCTRL clock
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pll_locked = Signal()
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pll_fb = Signal()
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pll_clk200 = Signal()
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# Actual MMCM/PLL instances
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=16.0,
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i_CLKIN1=clk125_div2,
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i_CLKFBIN=mmcm_fb,
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o_CLKFBOUT=mmcm_fb,
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o_LOCKED=mmcm_locked,
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# VCO @ 1.25GHz with MULT=20
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p_CLKFBOUT_MULT_F=20.0, p_DIVCLK_DIVIDE=1,
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# ~125MHz
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p_CLKOUT0_DIVIDE_F=10.0, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=mmcm_sys,
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# ~625MHz
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=mmcm_sys5x,
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# ~125MHz separated from sysclk, for RX
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p_CLKOUT2_DIVIDE=10, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=mmcm_rx_sys,
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# ~625MHz separated from sysclk, for RX
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=mmcm_rx_sys5x,
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# Leftovers...
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# p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=90.0, o_CLKOUT2=mmcm_sys4x_dqs,
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),
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Instance("PLLE2_BASE",
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p_CLKIN1_PERIOD=16.0,
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i_CLKIN1=clk125_div2,
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i_CLKFBIN=pll_fb,
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o_CLKFBOUT=pll_fb,
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o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
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# 200MHz for IDELAYCTRL
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p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk200,
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),
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]
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self.specials += [
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Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=mmcm_sys5x, o_O=self.cd_sys5x.clk),
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Instance("BUFG", i_I=mmcm_rx_sys, o_O=self.cd_rx_sys.clk),
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Instance("BUFG", i_I=mmcm_rx_sys5x, o_O=self.cd_rx_sys5x.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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# Add clock costraints for all clock signals
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platform.add_period_constraint(self.cd_sys.clk, 8.)
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platform.add_period_constraint(self.cd_sys5x.clk, 1.6)
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platform.add_period_constraint(self.cd_rx_sys.clk, 8.)
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platform.add_period_constraint(self.cd_rx_sys5x.clk, 1.6)
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platform.add_period_constraint(self.cd_clk200.clk, 5.)
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == DDLY}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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