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serdes-transceiver
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make debug mode

This commit is contained in:
occheung 2023-04-24 12:09:34 +08:00
parent 7035082d7f
commit b38a4d6b8c
1 changed files with 341 additions and 248 deletions
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153
single_serdes_loopback.py
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@ -12,7 +12,7 @@ from io_loopback import SingleIOLoopback
SEPARATOR = Constant(0b0101)
class SingleSerDesLoopBack(Module):
def __init__(self, io_pad, sys_clk_freq):
def __init__(self, io_pad, sys_clk_freq, debug):
self.uart_rx = Signal()
self.uart_tx = Signal()
@ -26,14 +26,17 @@ class SingleSerDesLoopBack(Module):
self.submodules.rx = SingleLineRX()
# Primary adjustment to master-slave bitslip
self.submodules.bitslip_reader = BitSlipReader()
self.submodules.slave_aligner = SlaveAligner()
self.submodules.post_align_reader = BitSlipReader()
# Optimal delay solver
self.submodules.phase_reader = PhaseReader()
self.submodules.delay_solver = DelayOptimizer()
# Debugging readers
if debug:
self.submodules.bitslip_reader = BitSlipReader()
self.submodules.post_align_reader = BitSlipReader()
self.submodules.phase_reader = PhaseReader()
# The actual channel
self.submodules.channel = SingleIOLoopback(io_pad)
@ -57,27 +60,39 @@ class SingleSerDesLoopBack(Module):
# Route deserializer to phase_reader & the delay tap optimizer
self.comb += [
# Start the reader initially
self.bitslip_reader.start.eq(1),
# Delay tap optimizer will start after the reader is done
self.slave_aligner.start.eq(0),
self.post_align_reader.start.eq(0),
self.phase_reader.start.eq(0),
self.delay_solver.start.eq(0),
# RXDATA for both reader and optimzer
self.bitslip_reader.loopback_rxdata.eq(self.rx.rxdata),
# RXDATA for aligner & optimzer
self.slave_aligner.loopback_rxdata.eq(self.rx.rxdata),
self.post_align_reader.loopback_rxdata.eq(self.rx.rxdata),
self.phase_reader.loopback_rxdata.eq(self.rx.rxdata),
self.delay_solver.loopback_rxdata.eq(self.rx.rxdata),
# Delay tap value
self.phase_reader.delay_tap.eq(self.rx.cnt_out),
self.delay_solver.delay_tap.eq(self.rx.cnt_out),
# IDELAY delay tap control, such that phase_reader can
# change tap value after delay measurement
self.rx.ce.eq(self.delay_solver.inc_en),
self.rx.master_bitslip.eq(self.slave_aligner.master_bitslip),
self.rx.slave_bitslip.eq(self.slave_aligner.slave_bitslip),
self.rx.ld.eq(self.delay_solver.ld),
self.rx.cnt_in.eq(self.delay_solver.opt_delay_tap),
]
# Debugging logics
if debug:
self.comb += [
# Start the reader initially
self.bitslip_reader.start.eq(1),
self.post_align_reader.start.eq(0),
self.phase_reader.start.eq(0),
self.bitslip_reader.loopback_rxdata.eq(self.rx.rxdata),
self.post_align_reader.loopback_rxdata.eq(self.rx.rxdata),
self.phase_reader.loopback_rxdata.eq(self.rx.rxdata),
self.phase_reader.delay_tap.eq(self.rx.cnt_out),
self.rx.ce.eq(
self.phase_reader.inc_en |
self.delay_solver.inc_en
@ -92,17 +107,107 @@ class SingleSerDesLoopBack(Module):
self.slave_aligner.slave_bitslip |
self.post_align_reader.bitslip
),
self.rx.ld.eq(self.delay_solver.ld),
self.rx.cnt_in.eq(self.delay_solver.opt_delay_tap),
]
# Show measured result on UART
if debug:
delay_tap_count = Signal(6)
bitslip_count = Signal(3)
post_align_bitslip_count = Signal(3)
rx_intra_aligned = Signal()
select_odd = Signal()
rxdata_decimated = Signal(5)
rxdata_pulse_read = Signal(10)
self.comb += [
If(select_odd,
rxdata_decimated.eq(self.rx.rxdata[1::2]),
).Else(
rxdata_decimated.eq(self.rx.rxdata[::2]),
),
]
if not debug:
release_fsm = FSM(reset_state="WAIT_ALIGNER")
self.submodules += release_fsm
release_fsm.act("WAIT_ALIGNER",
self.slave_aligner.start.eq(1),
If(self.slave_aligner.done,
NextState("WAIT_DELAY_OPT"),
),
)
release_fsm.act("WAIT_DELAY_OPT",
self.delay_solver.start.eq(1),
If(self.delay_solver.done,
NextValue(select_odd, self.delay_solver.select_odd),
NextState("INTRA_ALIGN_DONE"),
),
)
release_fsm.act("INTRA_ALIGN_DONE",
rx_intra_aligned.eq(1),
NextState("WAIT_TX_ZERO"),
)
release_fsm.act("WAIT_TX_ZERO",
If(rxdata_decimated == 0,
NextState("WAIT_PULSE"),
),
)
release_fsm.act("WAIT_PULSE",
If(rxdata_decimated != 0,
NextValue(rxdata_pulse_read, rxdata_decimated),
NextState("NEXT_RXDATA"),
),
)
next_rxdata = Signal(5)
release_fsm.act("NEXT_RXDATA",
NextValue(next_rxdata, rxdata_decimated),
NextState("WRITE_PULSE_UPPER"),
)
release_fsm.act("WRITE_PULSE_UPPER",
If(self.tx_fifo.writable,
self.tx_fifo.we.eq(1),
self.tx_fifo.din.eq(0),
NextState("WRITE_PULSE_LOWER"),
),
)
release_fsm.act("WRITE_PULSE_LOWER",
If(self.tx_fifo.writable,
self.tx_fifo.we.eq(1),
self.tx_fifo.din.eq(rxdata_pulse_read),
NextState("WRITE_NEXT_UPPER"),
),
)
release_fsm.act("WRITE_NEXT_UPPER",
If(self.tx_fifo.writable,
self.tx_fifo.we.eq(1),
self.tx_fifo.din.eq(0),
NextState("WRITE_NEXT_LOWER"),
),
)
release_fsm.act("WRITE_NEXT_LOWER",
If(self.tx_fifo.writable,
self.tx_fifo.we.eq(1),
self.tx_fifo.din.eq(next_rxdata),
NextState("TERMINATE"),
),
)
release_fsm.act("TERMINATE",
NextState("TERMINATE"),
)
else:
fsm = FSM(reset_state="WAIT_DONE")
self.submodules += fsm
@ -293,24 +398,12 @@ class SingleSerDesLoopBack(Module):
NextState("WAIT_TX_ZERO"),
)
rxdata_decimated = Signal(5)
self.comb += [
If(select_odd,
rxdata_decimated.eq(self.rx.rxdata[1::2]),
).Else(
rxdata_decimated.eq(self.rx.rxdata[::2]),
),
]
fsm.act("WAIT_TX_ZERO",
If(rxdata_decimated == 0,
NextState("WAIT_PULSE"),
),
)
rxdata_pulse_read = Signal(10)
fsm.act("WAIT_PULSE",
If(rxdata_decimated != 0,
NextValue(rxdata_pulse_read, rxdata_decimated),
@ -383,7 +476,7 @@ if __name__ == "__main__":
pad = platform.request("dio{}".format(eem), 0)
crg = KasliCRG(platform)
top = SingleSerDesLoopBack(pad, crg.sys_clk_freq)
top = SingleSerDesLoopBack(pad, crg.sys_clk_freq, False)
# Wire up UART core to the pads
uart_pads = platform.request("serial")