observe bit error

default.nix

@@ -7,8 +7,8 @@ let
         src = pkgs.fetchFromGitHub {
             owner = "m-labs";
             repo = "migen";
-            rev = "7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa";
+            rev = "ccaee68e14d3636e1d8fb2e0864dd89b1b1f7384";
-            sha256 = "039jk8y7f0vhr32svg3nd23i88c0bhws8ngxwk9bdznfxvhiy1h6";
+            sha256 = "sha256-oYdeY0MbTReKbAwmSznnqw0wNawdInJoFJVWW3tesFA=";
             fetchSubmodules = true;
         };
 

multi_serdes_loopback.py

@@ -77,15 +77,6 @@ class MultiSerDesLoopBack(Module):
         )
 
         self.rx_fsm.act("SAMPLE_RXDATA",
-            # If((sample_idx != 0) | (self.rx.rxdata != 0),
-            #     If(sample_idx == 15,
-            #         NextValue(sample_idx, 0),
-            #         NextState("WRITE_PATTERN_FIRST_UPPER"),
-            #     ).Else(
-            #         NextValue(sampled_rxdata[sample_idx], self.rx.rxdata),
-            #         NextValue(sample_idx, sample_idx + 1),
-            #     ),
-            # ),
             If(sample_idx == 15,
                 NextValue(sample_idx, 0),
                 NextState("WRITE_PATTERN_FIRST_UPPER"),
@@ -162,15 +153,31 @@ class MultiSerDesLoopBack(Module):
         self.tx_fsm.act("WAIT_GROUP_ALIGN",
             self.tx.txdata.eq(0),
             If(self.rx.delay_done,
-                NextState("SEND_ARB_DATA"),
+                NextState("SEND_ARB_DATA1"),
             ),
         )
 
-        self.tx_fsm.act("SEND_ARB_DATA",
+        self.tx_fsm.act("SEND_ARB_DATA1",
             self.tx.txdata.eq(0b00111001110011100111),
+            NextState("SEND_ARB_DATA2"),
+        )
+
+        self.tx_fsm.act("SEND_ARB_DATA2",
+            self.tx.txdata.eq(0),
+            NextState("SEND_ARB_DATA3"),
+        )
+
+        self.tx_fsm.act("SEND_ARB_DATA3",
+            self.tx.txdata.eq(0xDEADB),
+            NextState("SEND_ARB_DATA4"),
+        )
+
+        self.tx_fsm.act("SEND_ARB_DATA4",
+            self.tx.txdata.eq(0xBCAFE),
             NextState("TERMINATE"),
         )
 
+
         self.tx_fsm.act("TERMINATE",
             self.tx.txdata.eq(0),
             NextState("TERMINATE"),

single_serdes_loopback.py

@@ -473,7 +473,7 @@ if __name__ == "__main__":
     platform = kasli.Platform(hw_rev="v2.0")
 
     # Generate pads for the I/O blocks
-    eem = 2
+    eem = 1
     generate_pads(platform, eem)
     pad = platform.request("dio{}".format(eem), 0)
 

sync_serdes.py

@@ -208,7 +208,7 @@ class SlaveAligner(Module):
         self.master_bitslip = Signal()
         self.slave_bitslip = Signal()
 
-        self.slip_count = Signal(3)
+        slip_count = Signal(3)
 
         check_odd = Signal()
         check_even = Signal()
@@ -219,8 +219,6 @@ class SlaveAligner(Module):
         fsm.act("WAIT_START",
             If(self.start,
                 NextState("WAIT_TIMER"),
-            ).Else(
-                NextState("WAIT_START"),
             )
         )
 
@@ -243,7 +241,7 @@ class SlaveAligner(Module):
                 NextValue(check_even, self.loopback_rxdata[0]),
                 NextState("CHECK_MASTER_BITSLIP"),
             ).Else(
-                NextValue(self.slip_count, self.slip_count + 1),
+                NextValue(slip_count, slip_count + 1),
                 NextState("HIGH_BITSLIP_FIRST"),
             )
         )
@@ -265,7 +263,7 @@ class SlaveAligner(Module):
         fsm.act("HIGH_BITSLIP_SECOND",
             self.master_bitslip.eq(1),
             self.slave_bitslip.eq(1),
-            If(self.slip_count == 5,
+            If(slip_count == 5,
                 NextState("SHIFT_WAIT_TIMER"),
             ).Else(
                 NextState("WAIT_TIMER"),
@@ -322,7 +320,7 @@ class SlaveAligner(Module):
         )
 
         fsm.act("SHIFT_SAMPLE_PATTERN",
-            If((self.loopback_rxdata[3:4] != 0) & ~self.loopback_rxdata[5],
+            If((self.loopback_rxdata[3:5] != 0) & ~self.loopback_rxdata[5],
                 NextState("TERMINATE"),
             ).Else(
                 NextState("SHIFT_HIGH_BITSLIP_FIRST"),