123 lines
4.5 KiB
Python
123 lines
4.5 KiB
Python
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from migen import *
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class SerTX(Module):
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def __init__(self):
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self.txdata = Signal(20)
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self.ser_out = Signal(4)
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self.t_out = Signal(4)
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# TODO: Create T pins
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# Transmitter PHY: 4-wire
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for i in range(4):
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# Serialize 5 bits into each channel
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# TX SERDES
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self.specials += Instance("OSERDESE2",
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p_DATA_RATE_OQ="SDR", p_DATA_RATE_TQ="BUF",
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p_DATA_WIDTH=5, p_TRISTATE_WIDTH=1,
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p_INIT_OQ=0b00000,
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o_OQ=self.ser_out[i], o_TQ=self.t_out[i],
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i_RST=ResetSignal(),
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i_CLK=ClockSignal("sys5x"),
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i_CLKDIV=ClockSignal(),
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i_D1=self.txdata[i*5 + 0],
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i_D2=self.txdata[i*5 + 1],
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i_D3=self.txdata[i*5 + 2],
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i_D4=self.txdata[i*5 + 3],
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i_D5=self.txdata[i*5 + 4],
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i_TCE=1, i_OCE=1,
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# TODO: Hardcode t_in? Output disable is always unnecessary?
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i_T1=0)
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class DesRX(Module):
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def __init__(self):
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self.rxdata = Signal(20)
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self.ser_in = Signal(4)
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for i in range(4):
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# Deserialize 5 bits from each channel
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# RX SERDES
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self.specials += [
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Instance("ISERDESE2",
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p_DATA_RATE="SDR",
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p_DATA_WIDTH=5,
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p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
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o_Q1=self.rxdata[i*5 + 4],
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o_Q2=self.rxdata[i*5 + 3],
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o_Q3=self.rxdata[i*5 + 2],
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o_Q4=self.rxdata[i*5 + 1],
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o_Q5=self.rxdata[i*5 + 0],
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i_D=self.ser_in[i],
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i_CLK=ClockSignal("rx_sys5x"),
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i_CLKB=~ClockSignal("rx_sys5x"),
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i_CE1=1,
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i_RST=ResetSignal("rx_sys"),
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i_CLKDIV=ClockSignal("rx_sys")),
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# # Tunable delay
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# Instance("IDELAYE2",
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# p_DELAY_SRC="IDATAIN", p_SIGNAL_PATTERN="DATA",
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# p_CINVCTRL_SEL="FALSE", p_HIGH_PERFORMANCE_MODE="TRUE", p_REFCLK_FREQUENCY=200.0,
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# p_PIPE_SEL="FALSE", p_IDELAY_TYPE="VARIABLE", p_IDELAY_VALUE=0,
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# i_C=ClockSignal(),
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# i_LD=self._dly_sel.storage[i//8] & self._rdly_dq_rst.re,
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# i_CE=self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
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# i_LDPIPEEN=0, i_INC=1,
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# i_IDATAIN=dq_i_nodelay, o_DATAOUT=dq_i_delayed
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# )
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]
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# class DoubleDesRX(Module):
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# def __init__(self):
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# self.rxdata = Signal(20)
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# self.rx_first_edge = Signal()
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# rx_raw = Array(Signal(20) for _ in range(2))
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# self.comb += [
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# rxdata.eq(rx_raw[self.rx_first_edge])
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# ]
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# # Receiver PHY: 4-wire
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# for i in range(4):
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# # Deserialize 5 bits from each channel
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# # With 2x oversampling
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# # RX SERDES
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# self.specials += Instance("ISERDESE2", p_DATA_RATE="DDR",
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# p_DATA_WIDTH=10,
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# p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
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# p_SERDES_MODE="MASTER",
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# o_Q1=rx_raw[1][i*5 + 4], o_Q2=rx_raw[0][i*5 + 4],
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# o_Q3=rx_raw[1][i*5 + 3], o_Q4=rx_raw[0][i*5 + 3],
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# o_Q5=rx_raw[1][i*5 + 2], o_Q6=rx_raw[0][i*5 + 2],
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# o_Q7=rx_raw[1][i*5 + 1], o_Q8=rx_raw[0][i*5 + 1],
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# i_D=self.ser_in[i],
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# # We are using 5x for SDR
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# i_CLK=ClockSignal("sys5x"),
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# i_CLKB=~ClockSignal("sys5x"),
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# i_CE1=1,
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# i_RST=ResetSignal(),
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# i_CLKDIV=ClockSignal(),
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# o_SHIFTOUT1=serdes_link1,
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# o_SHIFTOUT2=serdes_link2)
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# self.specials += Instance("ISERDESE2", p_DATA_RATE="DDR",
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# p_DATA_WIDTH=10,
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# p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
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# p_SERDES_MODE="SLAVE",
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# o_Q1=rx_raw[1][i*5], o_Q2=rx_raw[0][i*5],
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# i_D=self.ser_in[i],
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# # We are using 5x for SDR
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# i_CLK=ClockSignal("sys5x"),
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# i_CLKB=~ClockSignal("sys5x"),
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# i_CE1=1,
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# i_RST=ResetSignal(),
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# i_CLKDIV=ClockSignal(),
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# i_SHIFTIN1=serdes_link1,
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# i_SHIFTIN2=serdes_link2)
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