103 lines
3.2 KiB
Python
103 lines
3.2 KiB
Python
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from migen import *
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from serdes import *
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from migen.genlib.fifo import SyncFIFO
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from migen.build.platforms.sinara import kasli
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from migen.genlib.misc import WaitTimer
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from kasli_crg import KasliCRG
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from eem_helpers import generate_pads
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from uart import UART
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from io_loopback import IOLoopBack
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SEPARATOR = Constant(0b0101)
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class SerDesLoopBack(Module):
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def __init__(self, io_pads, sys_clk_freq):
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self.uart_rx = Signal()
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self.uart_tx = Signal()
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self.submodules.uart = UART(round((115200/sys_clk_freq)*2**32))
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self.comb += [
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self.uart.phy_rx.eq(self.uart_rx),
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self.uart_tx.eq(self.uart.phy_tx),
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]
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self.submodules.tx = SerTX()
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self.submodules.rx = DesRX()
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# The actual channel
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self.submodules.channel = IOLoopBack(io_pads)
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# # Additional timer: Only permit UART transmission when timer is not up
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# self.submodules.wait_timer = WaitTimer(10)
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# Memoize the previous rxdata
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self.rxdata_r = Signal(8)
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# Attach FIFO to UART TX, send rate is too slow w.r.t sysclk
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self.submodules.tx_fifo = SyncFIFO(8, 64)
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self.comb += [
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# RX path: From UART to channel
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# self.rx_buffer.din.eq(self.uart.rx_data),
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# self.rx_buffer.we.eq(self.uart.rx_stb),
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self.tx.txdata[:8].eq(Mux(self.uart.rx_stb, self.uart.rx_data, 0)),
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self.tx.txdata[8:12].eq(Mux(SEPARATOR, self.uart.rx_data, 0)),
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self.tx.txdata[12:].eq(Mux(self.uart.rx_stb, self.uart.rx_data, 0)),
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# Loopback channel
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self.channel.i.eq(self.tx.ser_out),
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self.rx.ser_in.eq(self.channel.o),
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self.channel.t.eq(self.tx.t_out),
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# self.rx.ser_in.eq(self.tx.ser_out),
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# self.rx.ser_in[3].eq(self.tx.ser_out[3]),
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# TX path
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# self.uart.tx_data.eq(self.tx_buffer.dout),
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# self.uart.tx_stb.eq(self.tx_buffer.readable),
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# self.tx_buffer.re.eq(self.uart.tx_ack),
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self.uart.tx_data.eq(self.tx_fifo.dout),
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self.uart.tx_stb.eq(self.tx_fifo.readable),
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self.tx_fifo.re.eq(self.uart.tx_ack),
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]
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# Timer control
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self.sync += [
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# Send data to FIFO if not repeated
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If(self.rxdata_r != self.rx.rxdata[:8],
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self.rxdata_r.eq(self.rx.rxdata),
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self.tx_fifo.din.eq(self.rx.rxdata),
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self.tx_fifo.we.eq(1)
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).Else(
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self.tx_fifo.we.eq(0)
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)
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]
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# self.sync.sys5x += [
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# self.rx.ser_in.eq(self.tx.ser_out),
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# ]
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if __name__ == "__main__":
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platform = kasli.Platform(hw_rev="v2.0")
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# Generate pads for the I/O blocks
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eem = 0
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generate_pads(platform, eem)
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pads = [
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platform.request("dio{}".format(eem), i) for i in range(4)
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]
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crg = KasliCRG(platform)
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top = SerDesLoopBack(pads, crg.sys_clk_freq)
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# Wire up UART core to the pads
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uart_pads = platform.request("serial")
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top.comb += [
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top.uart_rx.eq(uart_pads.rx),
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uart_pads.tx.eq(top.uart_tx),
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]
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top.submodules += crg
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platform.build(top)
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