forked from M-Labs/nac3
Determine size_t using LLVM target machine
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266707df9d
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@ -24,6 +24,7 @@ use std::rc::Rc;
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use std::sync::Arc;
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use inkwell::{
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context::Context,
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memory_buffer::MemoryBuffer,
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module::{Linkage, Module},
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passes::PassBuilderOptions,
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@ -625,7 +626,9 @@ impl Nac3 {
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let buffer = buffer.as_slice().into();
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membuffer.lock().push(buffer);
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})));
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let size_t = if self.isa == Isa::Host { 64 } else { 32 };
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let size_t = Context::create()
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.ptr_sized_int_type(&self.get_llvm_target_machine().get_target_data(), None)
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.get_bit_width();
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let num_threads = if is_multithreaded() { 4 } else { 1 };
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let thread_names: Vec<String> = (0..num_threads).map(|_| "main".to_string()).collect();
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let threads: Vec<_> = thread_names
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@ -9,15 +9,11 @@
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#![allow(clippy::too_many_lines, clippy::wildcard_imports)]
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use clap::Parser;
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use inkwell::context::Context;
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use inkwell::{
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memory_buffer::MemoryBuffer, passes::PassBuilderOptions, support::is_multithreaded, targets::*,
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OptimizationLevel,
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};
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use parking_lot::{Mutex, RwLock};
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use std::collections::HashSet;
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use std::num::NonZeroUsize;
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use std::{collections::HashMap, fs, path::Path, sync::Arc};
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use nac3core::{
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codegen::{
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concrete_type::ConcreteTypeStore, irrt::load_irrt, CodeGenLLVMOptions,
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@ -39,6 +35,10 @@ use nac3parser::{
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ast::{Constant, Expr, ExprKind, StmtKind, StrRef},
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parser,
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};
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use parking_lot::{Mutex, RwLock};
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use std::collections::HashSet;
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use std::num::NonZeroUsize;
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use std::{collections::HashMap, fs, path::Path, sync::Arc};
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mod basic_symbol_resolver;
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use basic_symbol_resolver::*;
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@ -241,8 +241,6 @@ fn handle_assignment_pattern(
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}
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fn main() {
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const SIZE_T: u32 = usize::BITS;
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let cli = CommandLineArgs::parse();
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let CommandLineArgs { file_name, threads, opt_level, emit_llvm, triple, mcpu, target_features } =
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cli;
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@ -275,6 +273,24 @@ fn main() {
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_ => OptimizationLevel::Aggressive,
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};
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let target_machine_options = CodeGenTargetMachineOptions {
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triple,
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cpu: mcpu,
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features: target_features,
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reloc_mode: RelocMode::PIC,
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..host_target_machine
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};
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let size_t = Context::create()
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.ptr_sized_int_type(
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&target_machine_options
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.create_target_machine(opt_level)
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.map(|tm| tm.get_target_data())
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.unwrap(),
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None,
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)
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.get_bit_width();
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let program = match fs::read_to_string(file_name.clone()) {
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Ok(program) => program,
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Err(err) => {
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@ -283,9 +299,9 @@ fn main() {
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}
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};
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let primitive: PrimitiveStore = TopLevelComposer::make_primitives(SIZE_T).0;
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let primitive: PrimitiveStore = TopLevelComposer::make_primitives(size_t).0;
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let (mut composer, builtins_def, builtins_ty) =
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TopLevelComposer::new(vec![], ComposerConfig::default(), SIZE_T);
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TopLevelComposer::new(vec![], ComposerConfig::default(), size_t);
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let internal_resolver: Arc<ResolverInternal> = ResolverInternal {
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id_to_type: builtins_ty.into(),
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@ -373,16 +389,7 @@ fn main() {
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instance_to_stmt[""].clone()
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};
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let llvm_options = CodeGenLLVMOptions {
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opt_level,
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target: CodeGenTargetMachineOptions {
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triple,
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cpu: mcpu,
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features: target_features,
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reloc_mode: RelocMode::PIC,
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..host_target_machine
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},
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};
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let llvm_options = CodeGenLLVMOptions { opt_level, target: target_machine_options };
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let task = CodeGenTask {
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subst: Vec::default(),
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@ -405,7 +412,7 @@ fn main() {
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membuffer.lock().push(buffer);
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})));
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let threads = (0..threads)
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.map(|i| Box::new(DefaultCodeGenerator::new(format!("module{i}"), SIZE_T)))
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.map(|i| Box::new(DefaultCodeGenerator::new(format!("module{i}"), size_t)))
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.collect();
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let (registry, handles) = WorkerRegistry::create_workers(threads, top_level, &llvm_options, &f);
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registry.add_task(task);
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