nac3artiq/demo: get closer to regular ARTIQ

This commit is contained in:
Sebastien Bourdeauducq 2021-10-10 17:45:38 +08:00
parent a4ccac2329
commit 3a1dd893a1
3 changed files with 42 additions and 23 deletions

View File

@ -1,30 +1,24 @@
from min_artiq import * from min_artiq import *
from numpy import int32, int64
@kernel @kernel
class Demo: class Demo:
core: Core core: Core
led: TTLOut led: TTLOut
@portable
def __init__(self): def __init__(self):
self.core = Core() self.core = Core()
self.led = TTLOut(0) self.led = TTLOut(self.core, 19)
@kernel @kernel
def run(self): def run_k(self):
self.core.reset() self.core.reset()
while True: while True:
self.led.pulse_mu(int64(100000000)) self.led.pulse(100.*ms)
delay_mu(int64(True)) self.core.delay(100.*ms)
def run(self):
self.core.run(self.run_k)
@kernel
def testing(a: int32) -> int32:
return a + 1
if __name__ == "__main__": if __name__ == "__main__":
core = Core() Demo().run()
# core.run(testing, 1)
core.run(Demo().run)

View File

@ -7,10 +7,10 @@ device_db = {
"module": "artiq.coredevice.core", "module": "artiq.coredevice.core",
"class": "Core", "class": "Core",
"arguments": { "arguments": {
"host": "192.168.1.52", "host": "kc705",
"ref_period": 1e-9, "ref_period": 1e-9,
"ref_multiplier": 8, "ref_multiplier": 8,
"target": "cortexa9" "target": "riscv"
} }
}, },
} }

View File

@ -5,13 +5,13 @@ from numpy import int32, int64
import nac3artiq import nac3artiq
__all__ = ["KernelInvariant", "extern", "kernel", "portable", "ms", "us", "ns", "Core", "TTLOut"]
import device_db import device_db
core_arguments = device_db.device_db["core"]["arguments"]
nac3 = nac3artiq.NAC3(core_arguments["target"])
__all__ = ["KernelInvariant", "extern", "kernel", "portable", "Core", "TTLOut"]
nac3 = nac3artiq.NAC3(device_db.device_db["core"]["arguments"]["target"])
allow_module_registration = True allow_module_registration = True
registered_ids = set() registered_ids = set()
@ -55,6 +55,10 @@ def get_defined_class(method):
return vars(sys.modules[method.__module__])[method.__qualname__.split('.')[0]] return vars(sys.modules[method.__module__])[method.__qualname__.split('.')[0]]
ms = 1e-3
us = 1e-6
ns = 1e-9
@extern @extern
def rtio_init(): def rtio_init():
raise NotImplementedError("syscall not simulated") raise NotImplementedError("syscall not simulated")
@ -82,9 +86,10 @@ def rtio_input_data(channel: int32) -> int32:
@kernel @kernel
class Core: class Core:
@portable ref_period: float
def __init__(self): def __init__(self):
pass self.ref_period = core_arguments["ref_period"]
def run(self, method, *args, **kwargs): def run(self, method, *args, **kwargs):
global allow_module_registration global allow_module_registration
@ -112,14 +117,28 @@ class Core:
if now_mu() < min_now: if now_mu() < min_now:
at_mu(min_now) at_mu(min_now)
@portable
def seconds_to_mu(self, seconds: float) -> int64:
return int64(round(seconds/self.ref_period))
@portable
def mu_to_seconds(self, mu: int64) -> float:
return float(mu)*self.ref_period
@kernel
def delay(self, dt: float):
delay_mu(self.seconds_to_mu(dt))
@kernel @kernel
class TTLOut: class TTLOut:
core: Core
channel: int32 channel: int32
target_o: int32 target_o: int32
@portable @portable
def __init__(self, channel: int32): def __init__(self, core: Core, channel: int32):
self.core = core
self.channel = channel self.channel = channel
self.target_o = channel << 8 self.target_o = channel << 8
@ -144,3 +163,9 @@ class TTLOut:
self.on() self.on()
delay_mu(duration) delay_mu(duration)
self.off() self.off()
@kernel
def pulse(self, duration: float):
self.on()
self.core.delay(duration)
self.off()