forked from M-Labs/artiq
20e079a381
* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync * SUServo: Wrap CPLD and DDS devices in a list * SUServo: Refactor [nfc] Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk> Co-authored-by: David Nadlinger <code@klickverbot.at> |
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kasli | ||
kasli_drtioswitching | ||
kasli_sawgmaster | ||
kasli_suservo | ||
kc705_nist_clock | ||
metlino_sayma_ttl | ||
no_hardware | ||
sayma_master | ||
README.rst | ||
artiq_ipython_notebook.ipynb | ||
fit_image.py | ||
remote_exec_controller.py |
README.rst
ARTIQ experiment examples ========================= This directory contains several sample ARTIQ master configurations and associated experiments that illustrate basic usage of various hardware and software features. New users might want to peruse the ``no_hardware`` directory to explore the argument/dataset machinery without needing access to hardware, and the ``kc705_nist_clock`` directory for inspiration on how to coordinate between host and FPGA core device code.