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occheung
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artiq
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db3118b916
artiq
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artiq
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gateware
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rtio
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Sebastien Bourdeauducq
db3118b916
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
..
phy
rtio: Inout → InOut
2017-03-14 14:18:55 +08:00
__init__.py
rtio: export DMA and CRIInterconnectShared
2016-12-01 16:30:29 +08:00
analyzer.py
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
cdc.py
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
core.py
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
cri.py
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
dma.py
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
moninj.py
moninj: do not require a rsys clock domain
2017-02-20 15:52:48 +08:00
rtlink.py
rtio: add support for latency compensation in phy
2016-12-14 19:16:07 +01:00