Sebastien Bourdeauducq c656a53532 kc705: clean up clock constraints		2016-10-29 21:28:01 +08:00
..
amp	gateware: extend mailbox to 3 entries.	2016-10-21 12:09:14 +00:00
rtio	use new Migen signal attribute API	2016-10-29 21:19:58 +08:00
targets	kc705: clean up clock constraints	2016-10-29 21:28:01 +08:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9xxx.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc1.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
soc.py	gateware: extend mailbox to 3 entries.	2016-10-21 12:09:14 +00:00
spi.py	gateware/spi: fix import	2016-10-17 14:06:35 +08:00